setting single bit in std_logic_vector

[c_rpg]

I need to set and clear one bit in a large std_logic_vector, the position of the bit that needs to be changed is not static.

I have these signals:

signal large_vector : std_logic_vector(299 downto 0);
signal position        : std_logic_vector(8 downto 0);

And have tried:

large_vector(conv_integer(unsigned(signal position)))  <= '1';

But this doesn't work and I also think it will infer a latch because not all bits are assigned.

What is the proper way to set or clear this single bit?

 

[K-J]

I need to set and clear one bit in a large std_logic_vector, the position of the bit that needs to be changed is not static.

I have these signals:

signal large_vector : std_logic_vector(299 downto 0);
signal position        : std_logic_vector(8 downto 0);

And have tried:

large_vector(conv_integer(unsigned(signal position)))  <= '1';

But this doesn't work and I also think it will infer a latch because not all bits are assigned.

What is the proper way to set or clear this single bit?

What exactly do you see as 'not working'? Other than you're not using numeric_std the code you've posted will work just find for setting the particular bit that you want from 'large_vector'. What you're not showing though (and presumably the reason you rightly believe that a latch might be inferred) is the context in which the assignment to large_vector is being performed. Is it within a clocked process? Does the assignment need to be immediate (same clock cycle)? I'm guessing that the bits of large_vector can be put into a clocked process which would result in the following code

signal large_vector : std_logic_vector(299 downto 0);
signal position        : unsigned(8 downto 0);
-- Or consider this...
signal position        : integer range large_vector'range;  -- Specifies exactly the range that it should be
...
process(clk)
begin
  if rising_edge(clk) then
    if (reset = '1') then
      large_vector <= (others => '0'); -- Some reset value
    else
      large_vector(to_integer(position))  <= '1'; -- If signal_position is 'unsigned'
      large_vector(position)  <= '1'; -- If signal_position is 'integer', see it is a bit cleaner?
      ...
    end if;
  end if;
end process;

Kevin Jennings

 

[c_rpg]

Thanks for your reply.

The assignment is done in a clocked process like the one you've shown. What I meant with not working was in the specific context of my code. The large vector represents squares on a vga display. They wouldn't show up correctly, but I think the problem was incorrect initialization.

 

[std_match]

I need to set and clear one bit in a large std_logic_vector, the position of the bit that needs to be changed is not static.

What you are trying to do is not a problem for the VHDL language, but it can be a problem if you want to synthesize it into a real circuit.

If you are going to synthesize a circuit, you should have some idea about the necessary hardware.
To set or clear individual bits in a large vector sounds simple, but it requires a lot of logic.

You would never do it like that if you designed hardware the "old" way, by drawing a schematic.

The solution is to use a RAM. It already has all the logic you need to do this in a simple way.
The "position" will be used as the address.
RAM bits are quite cheap, so if your RAM is wider than one bit, it is probably OK to only use only one of them.

A RAM with one write port and one read port should be suitable for this.
I don't know about Xilinx, but Altera can have different data widths for the read and write ports.
In your case the write port should be one bit, but you probably want the read port to be wider, so you can access several bits at once.
If you want to have all bits available at the same time (as your original code), use several RAM blocks configured for the maximum bit width on the read port.
In that case you also need a decoder to select a RAM block when you write.