set_max_transition violation

[siva_7517]

set_max_transition

Hi there,

I encountered set_max_transition violation after the synthesis process in Design Compiler. I never specifed any set_max_transition constraint while doing synthesis process, because i dont have any idea what value to put in the constraint.
Need some help buddies....

Regards,
Siva

 

[deva_eda]

remove_from_collection

Siva,

You can check whatz the max transisition specified in the tech library if you check with your backend guys that you can increase the transistion time. Then you can over write the library max_trans with set_max_transition.

Further check if the output load on the violation pin is very high .. as you know output transition at pin is function of input transition and output load at the pin

 

[shiv_emf]

set_input_transition

DRC violation !! this may be due to high load on violated pin !... chking library mite help !

 

[funster]

how to set set_max_transition between clocks

even if you didn't set a max_transition value, in tech library, there is a default

value, you can set a more tight value.

Hi there,

I encountered set_max_transition violation after the synthesis process in Design Compiler. I never specifed any set_max_transition constraint while doing synthesis process, because i dont have any idea what value to put in the constraint.
Need some help buddies....

Regards,
Siva

 

[shiv_emf]

dc set max transition

even if you didn't set a max_transition value, in tech library, there is a default

value, you can set a more tight value.

Hi there,

I encountered set_max_transition violation after the synthesis process in Design Compiler. I never specifed any set_max_transition constraint while doing synthesis process, because i dont have any idea what value to put in the constraint.
Need some help buddies....

Regards,
Siva

without specifying constraint ..he is facing prob !!! nw if u give tighter constraint ..obviously thr will be violation
shiv

 

[siva_7517]

set_max_transition constraint violation

Hi,

Thanks for the feedbacks.....
I have checked the tech library and it says max_transition is 4.5
So, i have changed the set_load from 5 to 2...since the the output load should not be more then 4.5.
There is no violation after the synthesis process, but the violation occurs after the back end process.
the max_transition i got is 4.62 which is more then 4.5.

for better understanding, i have attached my constraint;

create_clock -p 25 clk

set_clock_latency 1 clk

set_clock_uncertainty -setup 1 [all_clocks]

set_clock_uncertainty -hold 0.15 [all_clocks]
set_input_transition 0.5 [remove_from_collection [all_inputs] [get_port clk]]

set_input_delay 12 -clock clk [remove_from_collection [all_inputs] [get_port clk]]

set_output_delay 5 -clock clk [all_outputs]

set_load 2 [all_clocks]

regards,
siva

 

[shiv_emf]

set_max_transition

try changing input transition !!! tht mite help

 

[rjainv]

how to set_max_transition

Hi,

Thanks for the feedbacks.....
I have checked the tech library and it says max_transition is 4.5
So, i have changed the set_load from 5 to 2...since the the output load should not be more then 4.5.
There is no violation after the synthesis process, but the violation occurs after the back end process.
the max_transition i got is 4.62 which is more then 4.5.

for better understanding, i have attached my constraint;

create_clock -p 25 clk

set_clock_latency 1 clk

set_clock_uncertainty -setup 1 [all_clocks]

set_clock_uncertainty -hold 0.15 [all_clocks]
set_input_transition 0.5 [remove_from_collection [all_inputs] [get_port clk]]

set_input_delay 12 -clock clk [remove_from_collection [all_inputs] [get_port clk]]

set_output_delay 5 -clock clk [all_outputs]

set_load 2 [all_clocks]

regards,
siva

If synthesis meets and max trans is violated in PnR, then synthesize with tighter constraint.

 

[energeticdin]

transistion violation

Hi Siva,

How to check the max-transition value in tech library..
what is the command to see?

Actually what is relationship between max_transition and set_load?
Plz tell me ?

 

[calm]

transition violation in synthesis

create_clock -p 25 clk

set_clock_latency 1 clk

set_clock_uncertainty -setup 1 [all_clocks]

set_clock_uncertainty -hold 0.15 [all_clocks]
set_input_transition 0.5 [remove_from_collection [all_inputs] [get_port clk]]

set_input_delay 12 -clock clk [remove_from_collection [all_inputs] [get_port clk]]

set_output_delay 5 -clock clk [all_outputs]

set_load 2 [all_clocks]

 

[red_boy]

remove_from_collection

I had better to fix the max-transistion violation in backend stage.

 

[siva_7517]

U can manually check in .lib file

 

[shiv_emf]

is ur prob solved/???????

 

[siva_7517]

Hi,

Thanks for the reply......
How we can relate set_max_transition and input_transition?
Im kinda of no clue on this.....

Siva

 

[sim_333]

set_max _transition is basically the max transition value that is set . A library can have this value set but u can also tighter this value.Now if some pins are violating this value then u ll have transition violations. So i think pin cannot drive that much high load , so if u try to reduce the load value probably it can help or upsize the buffer on that path which is having more driving strength. Input _transition is basically time a cell takes to change its value on a particular pin.

 

[phoenixfeng]

u can use set_max_fanout to decrease the pin load

 

[FLEXcertifydll]

pls show the path

 

[shiv_emf]

well u must be knowing the factors on which output transition depends !! plz check slow.lib library !!
u will find tables in thr

delay of cell depends on input transitio n output load !
shiv

 

[sekapr]

change to high drive strenght cell. Reducing the the set_load may not help because during placement the next gate will be placed too far away. In that case the tool will see more load and hence the vioilation still persists.

 

[deh_fuhrer]

the cell delay is generally function of input delay (transition delay) and output load.While doing synthesis EDA tool looks for max_transition attribute and then calculate the range of acceptable capacitance values from the delay table of the cell that can be connected at its output.