Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

set_fix_hold ,what means?

Status
Not open for further replies.

ls000rhb

Full Member level 3
Joined
Jun 17, 2005
Messages
185
Helped
7
Reputation
14
Reaction score
1
Trophy points
1,298
Activity points
2,425
set_fix_hold

set_fix_hold ,what means?i need to know how dc works when this command is added!
 

how to fix hold time violation in dc

set_fix_hold is a DC command that when added DC tries to fix hold violations through adding buffers mainly.
 

compile set_fix_hold

Through set_fix_hold command, DC tries to remove all the hold violations.
DC can insert buffers else it can try out different placements and can use some low drive strenght components also to delay the data signal.
 

set_fix_hold

Mostly the hold time fix process are done in the layout stage, not in the synthesis stage(such as SNPS DC).
 

DC try to fix hold violations in the clock domain.
 

yes ! DC will fix the holding violations of the clock domain !!
 

never do this if u have hold violations observed in pre-layout. unless otherwise u have hell lot of violations, dont do this in pre-layout.
in post-layout te hold vilations are fixed by beck-end. this is the best. dont think of minor hold in pre-layout
 

if this command is added,

DC will check each DFF's hold time to

find if there is violations,

if DC find violations, it will add delay buffer

before DFF's data input to fix hold time.

best regards




ls000rhb said:
set_fix_hold ,what means?i need to know how dc works when this command is added!
 

If you only want to fix design rule violations:
Do not use set_fix_hold

By default, DC does NOT fix hold time violations:
Use set_fix_hold to tell DC to fix hold time violations

Use compile –incr -only_design_rule:
DC only adds buffers or resizes cells
DC fixes only design rule violations and may fix hold time
violations
 

Mainly because of the notoriously inaccuracte of wireload model, adding
buffer in dc may doesn't make sense.However, if you wanna run presim
with timing , you canot do it with hold time violation.
 

but if run presim with hold violations, ur simulation will fail giving X.

adding buffer as roger said does not make sense in pre-layout.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top