Through set_fix_hold command, DC tries to remove all the hold violations.
DC can insert buffers else it can try out different placements and can use some low drive strenght components also to delay the data signal.
never do this if u have hold violations observed in pre-layout. unless otherwise u have hell lot of violations, dont do this in pre-layout.
in post-layout te hold vilations are fixed by beck-end. this is the best. dont think of minor hold in pre-layout
Mainly because of the notoriously inaccuracte of wireload model, adding
buffer in dc may doesn't make sense.However, if you wanna run presim
with timing , you canot do it with hold time violation.