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set input delay and set output delay

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veenashree89

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why do we subtract extrnal output delay with data required time ,in flipflop to output port path during setup analysis..?
 

childs

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Let's put it this way:
Data is always launch by a flop & captured by a flop. So in real life, data sent to output port is supposed to be captured by a flop outside of your design. Since the tool have no visibility of whatever outside the design, we assume a certain time will be consumed by anything starts from the design output port until the flop (outside the design). This amount of time is the external output delay that we set using "set_output_delay". Thus:

Slack = Data required time - [Data Arrival time (start flop to output port) + External Output Delay (output port to end flop outside design)]
=> Slack = [Data required time - External Output Delay (output port to end flop outside design)] - Data Arrival time (start flop to output port)

Hope my explanation is comprehensible.
 

veenashree89

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i got it :)

can u explain why we take minimum delay for hold analysis and maximum for setup analysis? and
why we give different uncertainity value for both setup and hold synthesis?
and reconvergence pessimism in STA
 

jeevan.life

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i got it :)

can u explain why we take minimum delay for hold analysis and maximum for setup analysis? and
why we give different uncertainity value for both setup and hold synthesis?
and reconvergence pessimism in STA

Im case of hold we are checking if data reaches too early or the best case that can exist in the design. So everything that can be done to violate hold, take min delay, uncertainity for paths etc is applied when we check for hold.

For setup we are checking for worst case or late data. So we try to violate the same way. Hope this is simple and gets you the point.


Reconvergence : When we have a common clock path between launch and capture flops, and when we apply the derates, launch must be fast and capture must be late to violate setup. But since there is a common path upto certain point, the logic in this common path cannot be fast and slow at the same time. So this common path pessimism is removed.
 

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