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sequentially means that the instruction you have written under process will run one by one...........
When some signal defined in the senstivity list will occour
sequentially means that the instruction you have written under process will run one by one...........
When some signal defined in the senstivity list will occour
With VHDL and Verilog you MODEL circuits NOT programe it. So the "Compiler" will choose the best aproach (or the one that it has) for that Behavoir and that's it.
The process is special because of the "sensitive" list.
Hope this help you, and please understand that you are Modeling rather than programming.
As your example is not have sensitivity list signal. So this process will always run.
In process, statement will calculate and update signal value at the end of process. So if first condition is not have any effect to second condition, your example seem to be parallel. The opposite way, if first condition effect to second one, it will show sequential as process meaning.
As your example is not have sensitivity list signal. So this process will always run.
In process, statement will calculate and update signal value at the end of process. So if first condition is not have any effect to second condition, your example seem to be parallel. The opposite way, if first condition effect to second one, it will show sequential as process meaning.
but regard the process have a senstive list ,like:
process( Clk,Rst)
-----
if x then
something
end if;
if y then
something1
end if;
end process;
So that is exactly what i dont understand : the process defined as sequential but
if the first condition is not have any effect to second condition, the example will be parallel so the process sometimes parralel and sometimes sequential ?
so what the meaning by saying the process is sequential
OK, as you new example. Clk and Rst is in sensitivity list, so this process will be execute at edge of Clk or Rst. At the edge only means that different time is -> 0.
I think you may not understand because you always use "signal" type? If you want to learn about sequential of process. You may try to make circuit by using "variable" instead.
"signal" type will be update value at the end of process. So you will see the output change seem to be parallel. But "variable" will update value immediately, so you can see effect of sequency.
OK, as you new example. Clk and Rst is in sensitivity list, so this process will be execute at edge of Clk or Rst. At the edge only means that different time is -> 0.
I think you may not understand because you always use "signal" type? If you want to learn about sequential of process. You may try to make circuit by using "variable" instead.
"signal" type will be update value at the end of process. So you will see the output change seem to be parallel. But "variable" will update value immediately, so you can see effect of sequency.
So if i understand what u write if i use "signal" and because it update value at the end of process the definition of sequential of process become actually to be parallel (but if i use variable the definition stay sequential )
try to make two processes , one for each if statement, each having clock in the sensitivity list, that's to have them parallel
but they can't change the same signal, take care of that
this will cause race conditions
but they will be sequential if they are in the same process
whether they are both true or not
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