Combinationa circuit can be derived from the always block with sensitivity list(inputs to the combi crkt) and all the assignments used in the always block should be blocking assignments.
Also the the logic derived from the assign statements is refered to be combi logic.
Sequential circuit can be derived from an always block with Clock edge and reset in the sensitivity list and all the statements should be nonblocking assignments(all the statements will trigger the output at triggering edge of the clock by using nonblocking assignments).
But in System verilog separate always constructs for seq and combi logic is prefered(always_ff -- Seq logic, always_comb -- combi logic)
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