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sequential code and combinational code in verilog

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alangs

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Am new to verilog.......somebody can give me some example code for sequential verilog code and combinational verilog code plz explain me how both works in always posedge of clock.....
 

Combinationa circuit can be derived from the always block with sensitivity list(inputs to the combi crkt) and all the assignments used in the always block should be blocking assignments.
Also the the logic derived from the assign statements is refered to be combi logic.


Sequential circuit can be derived from an always block with Clock edge and reset in the sensitivity list and all the statements should be nonblocking assignments(all the statements will trigger the output at triggering edge of the clock by using nonblocking assignments).

But in System verilog separate always constructs for seq and combi logic is prefered(always_ff -- Seq logic, always_comb -- combi logic)

--Thanks
 

I'll give u an example from a code i had written a while back. Note these both are abstract form from two different files :

//Eg for SEQUENTIAL LOGIC in Verilog

always @(posedge clock or negedge nReset) // check if you can make States
if (!nReset)
begin
DiceValue <= 1; // using <= here or =,
count <= 0;
end
else
case (DiceValue)
1: case (Ran) // oppsitie of 6
0: DiceValue<=3;
1: DiceValue<=2;
2: DiceValue<=5;
3: DiceValue<=4;
endcase

2: case (Ran) // oppsitie of 5
0: DiceValue<=3;
1: DiceValue<=6;
2: DiceValue<=1;
3: DiceValue<=4;
endcase


3: case (Ran) // oppsitie of 4
0: DiceValue<=5;
1: DiceValue<=6;
2: DiceValue<=1;
3: DiceValue<=2;
endcase

4: case (Ran) // oppsitie of 3
0: DiceValue<=2;
1: DiceValue<=1;
2: DiceValue<=6;
3: DiceValue<=5;
endcase

5: case (Ran) // oppsitie of 2
0: DiceValue<=4;
1: DiceValue<=1;
2: DiceValue<=6;
3: DiceValue<=3;
endcase

6: case (Ran) // oppsitie of 1
0: DiceValue<=4;
1: DiceValue<=5;
2: DiceValue<=2;
3: DiceValue<=3;
endcase
default: DiceValue=0; // define a default to avoid Latches
endcase



//COMBINATIONAL LOGIC

always @( DiceValue) // sensitivity list includes all the input parameters to which you want your "always" block to execute
begin
case(DiceValue)
0: begin
TL = 0; // LED for Zero
TR = 0; // using Blocking assignemnts ("=")for combinational logic
ML = 0;
MC = 0;
MR = 0;
BL = 0;
BR = 0;
end

1: begin
TL = 0; //LED for displaying 1
TR = 0;
ML = 0;
MC = 1;
MR = 0;
BL = 0;
BR = 0;
end

2: begin
TL = 0; // LED for displaying 2
TR = 1;
ML = 0;
MC = 0;
MR = 0;
BL = 1;
BR = 0;
end


3: begin
TL = 1; // LED for displaying 3
TR = 0;
ML = 0;
MC = 1;
MR = 0;
BL = 0;
BR = 1;
end

4: begin
TL = 1; // LED for displaying 4
TR = 1;
ML = 0;
MC = 0;
MR = 0;
BL = 1;
BR = 1;
end

5: begin
TL = 1; // LED for displaying 5
TR = 1;
ML = 0;
MC = 1;
MR = 0;
BL = 1;
BR = 1;
end

6: begin
TL = 1; // LED for displaying 6
TR = 1;
ML = 1;
MC = 0;
MR = 1;
BL = 1;
BR = 1;
end

7: begin // to use all the possible outcomes
TL = 1; // LED for displaying 7
TR = 1;
ML = 1;
MC = 1;
MR = 1;
BL = 1;
BR = 1;
end
// default : $display ("unknown Value");
endcase
end
 

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