shaiko
Advanced Member level 5
Hello,
I have a parallel, source synchronous video bus connected to my Altera FPGA.
IN_CLOCK (100MHz) is the clock signal and IN_DATA ( 11 downto 0 ) is the data synchronous to that clock. The access time of the video source data can be as high as 1ns according to the video device's documentation.
So, this is how I wrote my SDC constrains:
I started playing with the 1.000 value and increment it - just to see when the tool fails to meet the constrain.
From 1.000 I got up to 9.500 and still no failure.
Why is that ?
I have a parallel, source synchronous video bus connected to my Altera FPGA.
IN_CLOCK (100MHz) is the clock signal and IN_DATA ( 11 downto 0 ) is the data synchronous to that clock. The access time of the video source data can be as high as 1ns according to the video device's documentation.
So, this is how I wrote my SDC constrains:
Code:
create_clock -period 10 -waveform {0 5} -name IN_CLOCK [get_ports IN_CLOCK]
derive_pll_clocks # [B]The above clock drives a PLL and this PLL's output actually clocks the design[/B]
set_input_delay -clock IN_PCLOCK -max [COLOR="#FF0000"]1.000[/COLOR] [get_ports {IN_DATA*}]
I started playing with the 1.000 value and increment it - just to see when the tool fails to meet the constrain.
From 1.000 I got up to 9.500 and still no failure.
Why is that ?