Scaling down the resolution of VmodCam demo project, Atlys board

[Taki_comp]

Hi guys,
For those who worked with VmodCam
I am working on a project involving the implementation of real-time stereo vision system, for this purpose I am using the demo project provided by the digilent company to display video feeds on HDMI port
https://reference.digilentinc.com/_media/vmodcam/vmodcam_ref_hd_demo_13.zip
I tried to display the video feeds at the resolution of the project 1600x900, but the screen dipalys "HDMI not support" because the maximum resolution of the screen was 1366x768, for this reason I tried to scale down the resolution to 1280x720 so I did the following:
first of all, I modified the camera configuration as shown in the code below:

signal CamInitRAM: CamInitRAM_type := (
		IRD & x"30001580", -- Chip version. Default 0x1580

		IWR & x"33860501", -- MCU Reset
		IWR & x"33860500", -- MCU Release from reset
		
		IWR & x"32140D85", -- Slew rate control, PCLK 5, D 5

		IWR & x"341E8F0B", -- PLL control; bypassed, powered down
		IWR & x"341C0250", -- PLL dividers; M=80,N=2,fMCLK=fCLKIN*M/(N+1)/8=80MHz
		IWR & x"341E8F09", -- PLL control; Power-up PLL; wait 1ms after this!
		IWR & x"341E8F08", -- PLL control; Turn off bypass
		
		IWR & x"32020008", -- Standby control; Wake up

		IWR & x"338C2797", -- Output format; Context B shadow
		IWR & x"33900030", -- RGB with BT656 codes
		IWR & x"338C272F", -- Sensor Row Start Context B
		IWR & x"33900004", -- 4
		IWR & x"338C2733", -- Sensor Row End Context B
		IWR & x"339002DB", -- 1211, 731 => 2DB  Modified
		IWR & x"338C2731", -- Sensor Column Start Context B
		IWR & x"33900004", -- 4
		IWR & x"338C2735", -- Sensor Column End Context B
		IWR & x"3390050B", -- 1611, 1291 => 50B  modified
		IWR & x"338C2707", -- Output width; Context B
		IWR & x"33900500", -- 1600, 500 => 1280  modified
		IWR & x"338C2709", -- Output height; Context B
		IWR & x"339002D0", -- 1200,720=> 2D0 Modified
		IWR & x"338C275F", -- Crop X0; Context B
		IWR & x"33900000", -- 0
		IWR & x"338C2763", -- Crop Y0; Context B
		IWR & x"33900000", -- 0
		IWR & x"338C2761", -- Crop X1; Context B
		IWR & x"33900500", -- 1600, 1280 => 500  Modified
		IWR & x"338C2765", -- Crop Y1; Context B
		IWR & x"339002D0", -- 1200, 720=> 2D0 Modified 
      IWR & x"338C2741", -- Sensor_Fine_IT_min B
		IWR & x"33900169", -- 361 		

		IWR & x"338CA120", -- Capture mode options
		IWR & x"339000F2", -- Turn on AWB, AE, HG, Video
		
		IWR & x"338CA103", -- Refresh Sequencer Mode
		IWR & x"33900002", -- Capture
		IRD & x"33900000", -- Read until sequencer in mode 0 (run)
		
		IWR & x"301A02CC" -- reset/output control; parallel enable, drive pins, start streaming 		
		);
-- The modified lines are indicated with the word "modified"

One thing I don't get is how to change the " Sensor Row Start Context B" and " Sensor Row Start Context B", Actually I have no idea what they do mean.

I also modified the input resolution in the videotiming ctl as follows:

Inst_VideoTimingCtl: entity digilent.VideoTimingCtl PORT MAP (
		PCLK_I => PClk,
		RSEL_I => R1280_720P, --this project supports only 1280x720
		RST_I => VtcRst,
		VDE_O => VtcVde,
		HS_O => VtcHs,
		VS_O => VtcVs,
		HCNT_O => VtcHCnt,
		VCNT_O => VtcVCnt
	);

Finally, I modified the following writing address process for ports As follows

RADDRCNT_PROC_A: process (CLKA)
   begin
      if Rising_Edge(CLKA) then
			if (pa_int_rst = '1' and p1_wr_empty = '1') then
				pa_wr_addr <= 0;
         elsif (stateWrA = stWrCmd) then
				if (pa_wr_addr = 1280*720*2/(WR_BATCH*4)-1) then
					pa_wr_addr <= 0;
				else
					pa_wr_addr <= pa_wr_addr + 1;
				end if;
         end if;        
      end if;
   end process;
                                           
  WRADDRCNT_PROC_B: process (CLKB)
   begin
      if Rising_Edge(CLKB) then
			if (pb_int_rst = '1' and p2_wr_empty = '1') then
				pb_wr_addr <= 0;
         elsif (stateWrB = stWrCmd) then
				if (pb_wr_addr = 1280*720*2/(WR_BATCH*4)-1) then
					pb_wr_addr <= 0;
				else
					pb_wr_addr <= pb_wr_addr + 1;
				end if;
         end if;        
      end if;
   end process;

I believe that I made all the required modification in the vhdl code to scale down the resolution, unfortunately the on the screen was " HDMI Not support".
Can you please help me to debug the problem ?

 

[TrickyDicky]

Have you get a testbench? why cant you test it in simulation?

 

[Taki_comp]

The simulation will take very long time, and I am not sure whether changing some timing parameters will affect the result or It won't

- - - Updated - - -

Beisdes that, I simulate the input signals from VmodCam, It is a hard and time consuming task

 

[TrickyDicky]

I doubt this is a standard many people have experience with. Why cant you create a reference model for the input? when Ive simulated SDI in the past you can run an entire frame in a few minutes. I dont see why this should be any different.

 

[Taki_comp]

Did you use VmodCam before ?

- - - Updated - - -

I would like to understand what sensor row start is

 

[TrickyDicky]

Ive never even heard of VmodCAM, and it appears neither has most of the internet. Is it some proprietary 3d camera format? you might need to contact dilligent about how to use it as they seem to be the only people that make anything to do wtih it.

 

[Taki_comp]

If you have never heard of VmodCam, this does not mean that most of the internet did not, I am sure that most of people working in FPGA implementation of stereo vision system know about it, thank you for trying to be helpful

 

[TrickyDicky]

I am very confident that the numbers working on FPGA stereo vision systems are tiny/miniscule compared to the numbers working with standard video. You're very unlikely to get a reply to your specific problem, especially here. Google comes up with very limited hits - therefore it is has a very limited user base. The only real hit is a diligent board which only has reference designs for ISE 12/13 (so its at least 3 years old - https://reference.digilentinc.com/vmodcam/vmodcam) and another link says the board is now discontinued (https://store.digilentinc.com/vmodcam-stereo-camera-module-retired/)

reading the vmodcam reference manual (https://reference.digilentinc.com/_media/vmodcam/vmodcam_rm.pdf) the outputs are pretty straight forward and basically standard 422 YCbCr that you get on any SDI link or Various sized channels of RGB. So making a model of the input data provided from the VmodCam would be fairly straight forward.

You say that simulation of your VmodCam system takes "a long time". can you define how long? are you talking minutes, hours, days? Do you have simulation models for your interfaces? What are you trying to simulate?

I doubt anyone is going to post here that knows anything about VmodCam. You'll be better off trying to explain your problems and then maybe people here (who are experts in similar fields) may be able to help.