problem is tht i am not getting output correct.I am giving negatve going pulse to reset and posive pulse to clk and input .all unused pins like clr set and qb i have connected to vdd.i ma doing in cadence virtuoso.If any body has idea about please reply.
It is not allowed to connect an output to a fixed voltage. Often, the other output q is generated by inversion of qb.
Unused outputs have to be left open!
These signals come from your ADC. Don't know its structure - you should know it. CLK probably is your ADC clk, whereas SEL probably comes from the comparator output, see e.g. **broken link removed**
Reset means initialization. Necessary to initialize the SAR for correct operation and for testing. Just a single (neg. going) pulse before starting the ADC operation - probably identical to the ADC's reset.