sar adc design in cadence virtuoso

[ece04]

I am trying to make an sar adc.for sar logic i am using aynchronous d flipflop.i am using following circuit
https://obrazki.elektroda.pl/7371221100_1363591157.png

problem is tht i am not getting output correct.I am giving negatve going pulse to reset and posive pulse to clk and input .all unused pins like clr set and qb i have connected to vdd.i ma doing in cadence virtuoso.If any body has idea about please reply.

 

[erikl]

... and qb i have connected to vdd.

It is not allowed to connect an output to a fixed voltage. Often, the other output q is generated by inversion of qb.
Unused outputs have to be left open!

 

[ece04]

giving negative pulse to reset is it ok.or wht should i give as input to reset clk and input?

 

[erikl]

giving negative pulse to reset is it ok.

Sure!

... wht should i give as input to ... clk and input?

These signals come from your ADC. Don't know its structure - you should know it. CLK probably is your ADC clk, whereas SEL probably comes from the comparator output, see e.g. **broken link removed**

 

[ece04]

the output of the comparator is a digital pulse.The problem is with reset pin input?

 

[erikl]

The problem is with reset pin input

Reset means initialization. Necessary to initialize the SAR for correct operation and for testing. Just a single (neg. going) pulse before starting the ADC operation - probably identical to the ADC's reset.