ece04
Newbie level 4
I am trying to make an sar adc.for sar logic i am using aynchronous d flipflop.i am using following circuit
https://obrazki.elektroda.pl/7371221100_1363591157.png
problem is tht i am not getting output correct.I am giving negatve going pulse to reset and posive pulse to clk and input .all unused pins like clr set and qb i have connected to vdd.i ma doing in cadence virtuoso.If any body has idea about please reply.
https://obrazki.elektroda.pl/7371221100_1363591157.png
problem is tht i am not getting output correct.I am giving negatve going pulse to reset and posive pulse to clk and input .all unused pins like clr set and qb i have connected to vdd.i ma doing in cadence virtuoso.If any body has idea about please reply.