guow06
Junior Member level 3
my sample capacitor is 1pF and sample rate is 50MS/s. currently, I am using a boost-trapped switch.
I find it is so difficult to design such a switch that sample error is less than half LSB. Voltage drop due to charge injection is huge, and dummy transistor is used with few improvement. Any one can recommend a paper on 10-bit ADC with sample switch design? How do they do that in 12-bit or 10-bit 100MS/s ADC?
Few paper mention that, isn't is a difficult design part?
I find it is so difficult to design such a switch that sample error is less than half LSB. Voltage drop due to charge injection is huge, and dummy transistor is used with few improvement. Any one can recommend a paper on 10-bit ADC with sample switch design? How do they do that in 12-bit or 10-bit 100MS/s ADC?
Few paper mention that, isn't is a difficult design part?
