ahgu
Full Member level 3
I have 16bit data that comes in at 128MS/s, and I want to add 128 of them up at that rate, and then /128 after 128 samples.
Would you please recommend a FPGA or CPLD for that purpose. I don't need many IOs.
But the add performance is important. I would prefer XILINX, cost is important.
Would you please recommend a FPGA or CPLD for that purpose. I don't need many IOs.
But the add performance is important. I would prefer XILINX, cost is important.