A little bit confusing questions.
RTL - Register Transfer Level - The term is usualy used for the HDL code
BEFORE the synthesis, therefore its too early for the backannotation
Assuming gate level + .sdf after the synthesis, you need a characterized
timing library for your standard cells used for synthesis, typicaly Synopsys
.lib or CADENCE .tlf or .alf. The accuracy depends on the library, extractor
and how the .sdf is calculated.
For the transistor level simulation you just need the appropriate
transistor models and transistor level netlist in spice format.
.