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RTL sim with sdf v.s Circuit level spice simulation

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aramis

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rtl simulation vs trasistor simulation

Hi,
Can someone tell me what's the difference between the two types of simulation??
as i know, after synthesis and post layout, i can get the timing report and back annotation sdf file, and the gate level netlist.

Should i use the sdf file to simulate using Modelsim/Nc-sim in RTL level??
i can get more accurate timing to verify my RTL function work or not.

or,
i should use the gatelevel netlist to simuate using HSIM/Nanosim with the testbech??


What's the difference?? or Does it have relation with analog desgin??
I'm very confused.
please help me.



thanks

aramis
 

niko_zhang

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rtlsim

I think that the lib that you need is diferent for the two ways.
 

moorhuhn

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circuit level rtl

A little bit confusing questions.
RTL - Register Transfer Level - The term is usualy used for the HDL code
BEFORE the synthesis, therefore its too early for the backannotation
Assuming gate level + .sdf after the synthesis, you need a characterized
timing library for your standard cells used for synthesis, typicaly Synopsys
.lib or CADENCE .tlf or .alf. The accuracy depends on the library, extractor
and how the .sdf is calculated.
For the transistor level simulation you just need the appropriate
transistor models and transistor level netlist in spice format.

Transistor level simulation should be more accurate than gate level with
precharacterized libs BUT it is more time consuming or you decrease
the computing precision to have it faster and decrease also accuracy.
I would recommend to use gate level simulation for the tbench
verification and transistor level for some special cases, where you want
to exactly see whats going on. If you are going to use HSIM, you have
2 options. Either you simulate the extracted netlist with parasitics or
you use the T-level netlist and dspf. Anyway both of them are quite time
and memory consuming ...
 

aramis

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spice simulation using sdf file

moorhuhn said:
A little bit confusing questions.
RTL - Register Transfer Level - The term is usualy used for the HDL code
BEFORE the synthesis, therefore its too early for the backannotation
Assuming gate level + .sdf after the synthesis, you need a characterized
timing library for your standard cells used for synthesis, typicaly Synopsys
.lib or CADENCE .tlf or .alf. The accuracy depends on the library, extractor
and how the .sdf is calculated.
For the transistor level simulation you just need the appropriate
transistor models and transistor level netlist in spice format.
.


So, you mean that i should take synthesised gate level with the post-layout sdf timing to do simulation, that's will be enough for the usual case, right??

No need to do any transister level simulation, right??

thanks


aramis
 

moorhuhn

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spice to sdf

If you do just a digital design with an already proven library, you need not a T level simulation.
If you do mixed, high speed, full custom or not proven lib or io cells, you should use T level
simulation as a COMPLEMENT. Personaly, I am doing always T-level but never instead
of logic simulation with post-layout parasitics. :wink:
 

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