Resetting Signals in VHDL Combinational Process

[omara007]

vhdl combinational if

Hi folks

I have a combinational process, in which some signals are assigned values. I need a criteria to reset these signals before assigning them different values within the process. Is it possible to do the following:

if rst_n = '0' then
  x <= "000";
  y <= "00";
elsif enable = '1' then
  if state = state_0 then
     x <= "101";
     y <= "10";
  elsif state = state_1 then
     x <= "111";
     y <= "11";
  end if;
end if;

If so, when will the new values of (x) and be set ?

 

[sree205]

vhdl combinational loop

hi, its not necessary to assign defaults values w.r.t reset. you can follow this procedure.

always@(*)
x = "000";
y = "00;
if (enable=1)
x = "value";
y = "value";
elsif
rest of the assignment.

these values will be retained as long as the corresponding states r maintained.

cheers.

 

[omara007]

combinational process

hi, its not necessary to assign defaults values w.r.t reset. you can follow this procedure.

always@(*)
x = "000";
y = "00;
if (enable=1)
x = "value";
y = "value";
elsif
rest of the assignment.

these values will be retained as long as the corresponding states r maintained.

cheers.

This process will cause the x and y to be reset each time it's invoked.

 

[FvM]

I need a criteria to reset these signals before assigning them different values within the process.

I don't exactly understand what you want to achieve.

Generally the code infers latches respectively logig cell loops, because most CPLD or FPGA have no combinational latch hardware. You get a warning with most synthesis tools, cause latches are supposed to operate unreliable.

The most serious problem is to guarantee glitch-free latching signals. Particularly a multi-bit signal as state must be expected to go through undefined states during a transition. If state is changing with enable active, there's a high risk of unintended behaviour.

If you have any option to use synchronous logic instead, you should do.

 

[omara007]

I need a criteria to reset these signals before assigning them different values within the process.

I don't exactly understand what you want to achieve.

I want to be able to initialize a signal from inside a combinational process. So as, when an enable comes, this signal will already be of a certain initial value.

 

[FvM]

O.K. Reset isn't a problem, the code is possible. But depending on the timing of input signals state, enable and rst_n, it's not necessarily safe.

when will the new values of (x) and be set ?

The term set seems inadequate. The outputs are immediately changing according to input conditions and hopefully holding the previous state while enable is inactive.

Unfortunately, even the latter isn't guaranteed in a combinational loop circuit due to delay differences in logic cells.