May 4, 2006 #1 P preet Advanced Member level 4 Joined Jan 10, 2005 Messages 112 Helped 7 Reputation 14 Reaction score 5 Trophy points 1,298 Activity points 908 setup and hold time hello all, I want to know, whether the design specification would work for frequency divider? here are the specifications-- Qbar of the D flip flop is connected to Input D of the same D flipflop. setup time and hold time of the D flipflop is 2 nsec. clk to q and qbar is 1 nsec. I thought that there is hold time failure so the design should not work, is it correct? Regards Preet
setup and hold time hello all, I want to know, whether the design specification would work for frequency divider? here are the specifications-- Qbar of the D flip flop is connected to Input D of the same D flipflop. setup time and hold time of the D flipflop is 2 nsec. clk to q and qbar is 1 nsec. I thought that there is hold time failure so the design should not work, is it correct? Regards Preet
May 9, 2006 #2 O Ohh Member level 2 Joined May 31, 2001 Messages 50 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 440 I think, yes. But what is the interconnect (routing) delay between the QB output and the D input (of the same D-FF) ? If it is at least 1 ns long, it will not be the problem with the hold time requirement.
I think, yes. But what is the interconnect (routing) delay between the QB output and the D input (of the same D-FF) ? If it is at least 1 ns long, it will not be the problem with the hold time requirement.