regarding Setup and hold time

[preet]

setup and hold time

hello all,

I want to know, whether the design specification would work for frequency divider?
here are the specifications--

Qbar of the D flip flop is connected to Input D of the same D flipflop.

setup time and hold time of the D flipflop is 2 nsec.
clk to q and qbar is 1 nsec.

I thought that there is hold time failure so the design should not work, is it correct?

Regards

Preet

 

[Ohh]

I think, yes.

But what is the interconnect (routing) delay between the QB output and the D input (of the same D-FF) ?
If it is at least 1 ns long, it will not be the problem with the hold time requirement.