design compiler, compile path group
hai energitic,
small mistake in your script in path group specification..
group_path -name pathsout -critical_range 3.0 -from [all_outputs]
It should be
group_path -name pathsout -critical_range 3.0 -to [all_outputs]
because , outputs are endpoints. There wont be any paths from output ports. All the paths end at output port. DC doesnt recognize this path group and its take it in the clock/register path group. so your critical range doesnt consider for this path group..Try modifying this. it may solve your problem.
Regarding low drive strengths ,In the library, cells with 0.5x,1x,2x,3x.....10x drive strength cells are avaialble. Low drive strength cells will consume more delay and it will create timing problems at initial stages. Initially try to put set_dont_use on these cells . After analyzing for final synthesis , you can remove this set_dont use in your script..
let me know any issues ..
Regards,
Sam