amjad163
Newbie level 5
Hi,
I read couple of earlier posts but they dint answer the current question completely. Hence I am posting this question:
If we look at this website Wire And Reg In Verilog, the synthesized output for the first two modules is the same, irrespective of if y was declared as reg or wire. Can any one tell me why you would use one approach over the other if there is no difference in synthesis.
Thanks,
Amjad
I read couple of earlier posts but they dint answer the current question completely. Hence I am posting this question:
If we look at this website Wire And Reg In Verilog, the synthesized output for the first two modules is the same, irrespective of if y was declared as reg or wire. Can any one tell me why you would use one approach over the other if there is no difference in synthesis.
Thanks,
Amjad