reg wire difference in combinational circuit...

[amjad163]

Hi,

I read couple of earlier posts but they dint answer the current question completely. Hence I am posting this question:

If we look at this website Wire And Reg In Verilog, the synthesized output for the first two modules is the same, irrespective of if y was declared as reg or wire. Can any one tell me why you would use one approach over the other if there is no difference in synthesis.

Thanks,
Amjad

 

[bala_EE]

I too have the same question. I dont really understand the difference between them... Looking forward to understanding them in this post...

 

[ebuddy]

It is confusing for people who are learning the language. But just remember a couple of things:
1. in always block, everything on LHS has to be declared as reg.
2. in continous assignment, LHS can only be declared as wire.

These are just language requirement, which at the time when the language was invented, might make sense. In the actual circuit, a physical wire can come from either a "wire" type signal or a "reg" type signal.

 

[amjad163]

thanks ebuddy. so its just the requirement of the language..

 

[sam33r]

A small addition.
In test fixture everything is declared as reg except o/p which are declared as wire

 

[bala_EE]

A small addition.
In test fixture everything is declared as reg except o/p which are declared as wire

Why do we do that? Why is it that testbenches have regs as inputs and instances have wires as inputs?

 

[RBB]

A small addition.
In test fixture everything is declared as reg except o/p which are declared as wire

Not necessarily.

 

[bala_EE]

Not necessarily.

Lets say you have clk as input in a test module. We have to put some logic which imitates a clock signal. Something like....

always
$10 clk <= ~clk;

How can we use clk as a wire, if clk is in the LHS and is in an always block? We have to use clk as reg.

 

[RBB]

Lets say you have clk as input in a test module. We have to put some logic which imitates a clock signal. Something like....

sam33r stated every signal besides outputs must be declared as regs. That's not true. You can use wires as well.

 

[bala_EE]

Can you please tell me why we use reg and wire in one manner in testbenches and why is it used in the opposite manner in the instances?

 

[RBB]

Most cases you would use regs to drive inputs to your DUT. However if your DUT pin is an inout, then you'd need to drive it with a wire..

wire a;
reg aReg;

assign a = aReg;

foo DUT(.A(a));

initial
  begin
    aReg = 1'bz;
    #100 aReg = 1'b1;
    #100 aReg = 1'b0;
    #100 aReg = 1'bz;
  end

 

[bala_EE]

Can you explain why?

 

[RBB]

You can't use a reg to drive a bi-directional. Rules of Verilog.

 

[bala_EE]

So, everytime we use a reg or wire, the only reason we are doing so, is that, those are the rules of verilog and there is no other reason or explanation behind it. Is that so?

 

[RBB]

Not necessarily. In the link in the first post it shows two code snippets: one coded with reg & one coded with wire, but both produce the same behavior. In that case it really comes down to coding style; preference and/or readability on which one to use. Also you may see a slight simulator performance difference between the assign/wire & always @/reg snippets.

 

[sam33r]

Test benches are not synthesized, hence the output is always wire. Inout is an exception as RBB stated.

 

[vs21]

Keep it simple....

IF you are doing a assignment inside a always block, use 'reg' for the signal ELSE use 'wire'.

Thats it.

 

[bsbs]

reg variables can be used both in combinational and sequential .
Reg components are a must for sequential modelling as drivability is necessary(same reasons for output being reg in some cases)
In case of test benches inputs of UUT must be driven and output is wire because reg elements cannot be connected to output port of module instantiation.
You will understand it better if you draw a block diagram of the component with the input , output signals and ports connected to them inside and outside the block ,thus helping in identifying the type wire or reg