I read couple of earlier posts but they dint answer the current question completely. Hence I am posting this question:
If we look at this website Wire And Reg In Verilog, the synthesized output for the first two modules is the same, irrespective of if y was declared as reg or wire. Can any one tell me why you would use one approach over the other if there is no difference in synthesis.
It is confusing for people who are learning the language. But just remember a couple of things:
1. in always block, everything on LHS has to be declared as reg.
2. in continous assignment, LHS can only be declared as wire.
These are just language requirement, which at the time when the language was invented, might make sense. In the actual circuit, a physical wire can come from either a "wire" type signal or a "reg" type signal.
So, everytime we use a reg or wire, the only reason we are doing so, is that, those are the rules of verilog and there is no other reason or explanation behind it. Is that so?
Not necessarily. In the link in the first post it shows two code snippets: one coded with reg & one coded with wire, but both produce the same behavior. In that case it really comes down to coding style; preference and/or readability on which one to use. Also you may see a slight simulator performance difference between the assign/wire & always @/reg snippets.
reg variables can be used both in combinational and sequential .
Reg components are a must for sequential modelling as drivability is necessary(same reasons for output being reg in some cases)
In case of test benches inputs of UUT must be driven and output is wire because reg elements cannot be connected to output port of module instantiation.
You will understand it better if you draw a block diagram of the component with the input , output signals and ports connected to them inside and outside the block ,thus helping in identifying the type wire or reg