read_parasitics and set load

[Wenf.Yeh]

when I using PrimePower for Gate-Level Power Estimation
I think should read SPEF or DSPF format parasitics file in the Post-layout situation
but int the Pre-Layout circumstance, must I use the command "set_load" to set the capacitance and resistance information for the Power Estimation.

 

[subos]

I want to ask this question too.

For the pre-layout power analysis, someone suggests to use "set_load" command to specify the amount of capacitance on the high fanout nets such as clock net. However, how to get the capacitance value set for the clock net?

Added after 8 minutes:

Below is the way to calcuate the capacitance described in PrimePower Manual:


//
Calculating the Capacitance of a Net
To calculate the capacitance of a net,

Determine the fanout of the net.

Look up the length from the fanout_length pairs in the wire_load model.

Calculate the capacitance by multiplying the length by the capacitance coefficient.

Example

wire_load("90x90") {capacitance : 2.0 ; /* C per unit-length */resistance :100.0 ; /* R per unit-length */area : 0.5 ; /* net-area per unit-length */slope : 1.5 ; /* extrapolation slope */fanout_length(1,1) ; /* fanout_length pairs */fanout_length(2,2.2);fanout_length(3,3.3);fanout_length(4,4.4);

}

To determine lumped net capacitance, total net resistance, and the design area due to the net, PrimePower multiplies the capacitance, resistance, and area scaling factors by the estimated wire length.

PrimePower calculates the net fanout value as the total number of pins on the net excluding one driver pin. For example, on a net with 2 fanin pins and 3 fanout pins, the fanout value is

(2 + 3) - 1 = 4

The lumped net capacitance is calculated by multiplication of the estimated wire length by the capacitance factor 2.0. For a fanout value of 4, the last fanout_length defines the wire length as 4.4, resulting in a calculated lumped net capacitance of

2.0 * 4.4 = 8.8

The total net resistance is calculated by multiplication of the estimated wire length by the resistance factor, yielding a value of

4.4 * 100.0 = 440.0

When calculating pin-to-pin RC delays, PrimePower interprets the total net resistance on the basis of the current operating condition’s tree_type attribute.
//


Can I use the way to calculate the capacitance for the clock net because I can get the fanout of clock net from the synthesis reports?