Yes, by all means. Unless you want to read the same data as you are writing, on the same clock, then you need to have a 'bypass' method. In all other cases no special treatemnet is needed.
signal rd_wr_reg : std_logic_vector(n downto 0);
.
.
for writing you will need a clocked process
wr_process_clk_p : process(clk)
begin
if(rising_edge(clk)) then
rd_wr_reg <= write_data;
end if;
end process wr_process_clk_p;
for reading, you can just say
read_data <= rd_wr_reg;
or you may have your read_data as another register, in which
you would like to capture the rd_wr_reg, then
rd_process_clk_p : process(clk)
begin
if(rising_edge(clk)) then
read_data <= rd_wr_reg;
end if;
end process rd_process_clk_p;
Hope it helps,
Kr,
avi
http://www.vlsiip.com