Read and write operations issue?

[premkiran]

Hello,

is it possible to perform read and write on the same Register (arbitrary width) with out any issue in a single clock period.
( order of read and write operations ,issued are important)

pleae explain your remarks

thank you
premkiran

 

[avimit]

Yes, by all means. Unless you want to read the same data as you are writing, on the same clock, then you need to have a 'bypass' method. In all other cases no special treatemnet is needed.

signal rd_wr_reg : std_logic_vector(n downto 0);

.
.
for writing you will need a clocked process
wr_process_clk_p : process(clk)
begin
if(rising_edge(clk)) then
rd_wr_reg <= write_data;
end if;
end process wr_process_clk_p;

for reading, you can just say
read_data <= rd_wr_reg;

or you may have your read_data as another register, in which
you would like to capture the rd_wr_reg, then

rd_process_clk_p : process(clk)
begin
if(rising_edge(clk)) then
read_data <= rd_wr_reg;
end if;
end process rd_process_clk_p;

Hope it helps,
Kr,
avi
http://www.vlsiip.com

 

[pintuinvlsi]

I just want to something on above reply
If your write and read are both synchronous i.e with respect to clock edge, then during reading the register you will get older value of register, written value you will get in next cycle only.

 

[megastar007]

What pintuinvlsi has said is correct and it is expected behavior. Otherwise you can directly read what you are wrting so that you have both vlaues same. But doesnt make sense in real design

 

[ubna]

Its highly possible for registers. But when you try this in a ram memory, i am afraid its not possible....

 

[longsun]

Register could be constructed with Latch or Flop. Both of them have input D and output Q ports. Do the read and write at same cycle is not a problem. Read out the same data as written or the old data is depend on the time read data get strobe out.
Dual port RAM has two type synchronous and asynchronous. The RAM spec will specify what happen when write and read at same cycle.