andrew257
Member level 2
if i make a test bench and instantiate a top module i do not get any change in waveforms. They all stay to what they are initialised to.
my top module has three modules instantiated into it. Does that mean my test bench needs all three sub modules for it to work. i was under the impression only the top module needs to be included in testbench.
all sub modules simulate and work as designed. Just when i bring them together into one module i cant get anything to change.
my top module has three modules instantiated into it. Does that mean my test bench needs all three sub modules for it to work. i was under the impression only the top module needs to be included in testbench.
all sub modules simulate and work as designed. Just when i bring them together into one module i cant get anything to change.