Questions about submodels of instantiated top model in testbench

[andrew257]

if i make a test bench and instantiate a top module i do not get any change in waveforms. They all stay to what they are initialised to.

my top module has three modules instantiated into it. Does that mean my test bench needs all three sub modules for it to work. i was under the impression only the top module needs to be included in testbench.

all sub modules simulate and work as designed. Just when i bring them together into one module i cant get anything to change.

 

[echo47]

testbench

I assume you are referring to VHDL or Verilog.

Your approach sounds good. I normally instantiate only the top module into my test bench.
You may have a small bug that's causing a malfunction. If you need help debugging it, show us the code.

 

[Tom2]

Re: testbench

Is is possiple to give an example create testbench in vhdl using for loop??

 

[soloktanjung]

Re: testbench

hi,

this is for loop using verilog. hope u get the idea hoe to do this is vhdl.

----------------------------------------------------------------
module mux41nonblockTB_v;

// Inputs
reg [1:0] sel;
reg [3:0] a;

// Outputs
wire b;

// Instantiate the Unit Under Test (UUT)
mux41nonblock uut (
.sel(sel),
.a(a),
.b(b)
);

integer i,j;
initial begin
// Initialize Inputs
a=4'd0;
sel=2'd0;

for(i=0;i<16;i=i+1)
for(j=0;j<4;j=j+1)
begin
a=i;
sel=j;
#50;
$display("time=%t, input=%b,select=%b,output=%b", $time, a, sel, b);
end
end

endmodule
------------------------------------------------------------------------------

regards,
hairo

 

[Nikolai]

Re: testbench

If you are using Xilinx ISE (or any other for that matter), the project might be containing only the top level module. although there is no error during compilation, the simulaiton is not satisfactory. Make sure u manually add the sub modules too in the design. i.e right click and add file.

and yes, the testbench should be associated with the top level module.

 

[sanchu]

Re: testbench

Only instantiating top module will do. No need to have submodules in your testbench.