Questions about designing LDO

[quaternion]

Re: LDO questuionair???

... but in a recent design wich i did i had a ground current of few hundred nA in resistive feedbak and less than a uA of ground current in EA and its bias.

Could you tell me about the specs of such design ,specially the transient and drop out ones, please.

Also I have a related question: If the EA stage that drives the pass element is loaded by a diode connected PMOS transistor ,are their constrains on the size of this diode connected transistor [as in this case the configuration appears to be as if this diode connected transistor mirrors current to the pass element , and what I know is that for current mirrors there are constrains for good matching; should we violate these constrains or what ? ]

 

[ashish_chauhan]

Re: LDO questuionair???

Firstly let me update ... the numbers which i stated were for standby mode or ow power mode...

Secondly I could not understand Why are you talking of a diode connected device loading the EA output... I dont have any such device in my design...

In normal mode my EA consumes around 10~12uA, leakage in resistive feedback remains the same.

Sorry as i cannot reveal the specs till the silicon is out.

 

[quaternion]

Re: LDO questuionair???

Secondly I could not understand Why are you talking of a diode connected device loading the EA output... I dont have any such device in my design...

In normal mode my EA consumes around 10~12uA, leakage in resistive feedback remains the same.

Sorry as i cannot reveal the specs till the silicon is out.

I mean the diode connected near the pass element (for example) in the schematic attached at

In normal mode my EA consumes around 10~12uA, leakage in resistive feedback remains the same.
Sorry as i cannot reveal the specs till the silicon is out.

I had asked for such specs in order to estimate a reasonable spec for ground current in my design as I have 0.1V drop out , 5mA max out current , and 0.12V maximum spike-or dip-and the ground current isn't determined .So I had asked in order to estimate a spec to put for my self(this is for an educational project & only design is done & no final fabr.). So could you suggest a reasonable value according to these specs.

 

[ashish_chauhan]

Re: LDO questuionair???

quatarnion whats the value of ur output cap...? and ur total current budget?

 

[quaternion]

Re: LDO questuionair???

Maximum value for output Cap is 100pF (on chip Cap) and maximum output current is 5mA, And I want to assume a reasonable value for the ground current (I guess it will be small ; the problem is that I should regulate a crystal osc load that drives a current in the MHz range :| )

 

[rajanarender_suram]

Re: LDO questuionair???

As you can see in the figure:

no load UGB of the LDO system is less then P1(due to output external cap).

So if i have to introduce a ESR zero and P2 (due to EA ; as i cannot keep P2 occuring beyond the UGB of full load) i have to introduce them beyond P1.... is it True for the system????

what are the effects of having less UGB for no load ?? and how can i improve it????

 

[quaternion]

Re: LDO questuionair???

no load UGB of the LDO system is less then P1(due to output external cap).

I think that isn't true , or you mean P1(at no load )is at very small frequency such that UGB(no load) < P1(full load) ?

what are the effects of having less UGB for no load ?? and how can i improve it????

(if the LDO is stable)
I think if this is due to your output cap then it seems to be large enough that it catches transients & PSRR well.

 

[rajanarender_suram]

Re: LDO questuionair???

........ you mean P1(at no load )is at very small frequency such that UGB(no load) < P1(full load) ?

Yes

what are the effects of having less UGB for no load ?? and how can i improve it????

(if the LDO is stable)
I think if this is due to your output cap then it seems to be large enough that it catches transients & PSRR well.

??? i did not got the point

 

[quaternion]

Re: LDO questuionair???

I mean since your dominant pole is at very low frequency but you have a large gain so the low frequency PSRR should be OK &the PSRR will rise (reduced as a value) at relatively small frequency but starting originally from a very good PSRR, taking the output cap into consideration the output cap should take care of high frequency PSRR (as you are using a large out cap);So it seems that an effect has canceled the other large gain at low frequency & moderate gain at higher frequency= that is what I mean by PSRR is well.
While for transient I think you are depending strongly on the out put cap so it mayn't be affected at all, depending on the cap value.

These are my expectations , may be some are not right ,I need confirmation.

 

[rajanarender_suram]

LDO questuionair???

can i keep the freq response of LDO as shown in the figure???

or should i make the UGB of no load go beyond P1 so that i can introduce another pole (due to EA ) and zero(esr) in the common region and still can increase my UGB

 

[ashish_chauhan]

Re: LDO questuionair???

freq response for noload is absolutely fine... (I am assuming you have enaough phase margin in this case... around 90 deg)

Low ugb wont really effect the performance of ldo coz in low load conditions(generally) there are not much variations of load... so having low ugb (which means a slower response time) wont have a problem.

for full load you have good ugb so again... no probs!!!

Added after 4 minutes:

quaternion -

i saw the schematic of ur ldo(capless) how much current are you burning in quescient state...?

It appears like u are trying to add a zero in the transfer function of loop gain...

and also I cud not see the 2 "RHP zeros".

 

[quaternion]

Re: LDO questuionair???

i saw the schematic of ur ldo(capless) how much current are you burning in quescient state...?

I want to note that I had made other circuits (~ 10 cts) in order to get a performance near to the needed one.
The quescient current isn't small (indeed I need it to be fast), it is around 200uA some times more and sometimes less.

It appears like u are trying to add a zero in the transfer function of loop gain...

Yes I am tring to add a left half plane zero that elevates the phase shift up again.

and also I cud not see the 2 "RHP zeros".

I am not understanding ,I didn't mention RHP zeros ,do you mean the parasitic ones, or you mean you couldn't see the the effect of the LHP zeros in the loop gain?

 

[ashish_chauhan]

Re: LDO questuionair???

Then I think you made a typo eror in "loop stability" post where u said maybe its due to the two RHP zeroes... (just check over there)

 

[quaternion]

Re: LDO questuionair???

Actually I said two RHP poles, and after this I discovered that this is right from the pole zero analysis (attached there).

 

[ashish_chauhan]

Re: LDO questuionair???

Are they(rhp poles) inside ur UGB...?

If yes then ur system is potentially unstable(I know you know that)

You said ur reg is supposed to supply a pll working at freqs of 22Mnz to 1.9Ghz...

Do you really need a loop bandwidth in that range...or just a high psrr in those freq ranges wud do?

I did a reg (capless) for pll in my previous firm ... the pll was supposed to work at some 400Mhz... but ny loop bandwidth was only 3Mhz. but it had a psrr of 40dB+ in the freqs of pll range.

and the design is working on silicon.
so just analyse if u really need a very high UGB.

 

[quaternion]

Re: LDO questuionair???

yes I only needs a PSRR that is good in that range and to achieve this I need to extend my UGB to the extent that catches the PSRR due to the output cap.(i.e. the worst point PSRR is enhanced), and so I need to achieve UGB of 10MHz.


I have a question about the output on chip cap , what is the ordinary used type for ldo (100pF) MIM will take a huge space and MOScap will generate large flicker noise ??

 

[ashish_chauhan]

Re: LDO questuionair???

I used a moscap only... no mimcaps...

 

[quaternion]

Re: LDO questuionair???

And what about compensation cap(s) ? (MOScap or MIM ? or depending on the capacitance value)

 

[ashish_chauhan]

Re: LDO questuionair???

well yes the appropriate answer is " it depends"

but I usually go with mos caps..