Questions about designing LDO

[ashish_chauhan]

Re: LDO questuionair???

what is the error ur spec allows ... from that calculate the loopgain requiered.

60dB is good enough... just check for the ugf ... 10k is not good.(Typically, rest depends on the transient specs.)

 

[rajanarender_suram]

LDO questuionair???

ugf is 10Meg...

Added after 2 minutes:

as i see in the model simulations .. the error majorly depends on EA gain rather than loop gain..


the ugf sepcified with Cout 1uf cap>>>

 

[jecyhale]

Re: LDO questuionair???

what is the region of operation of pass element in LDO

I thinks saturation is the best.
Because it can provide a large current range if it is in saturation region.

 

[rajanarender_suram]

LDO questuionair???

what is the error ur spec allows ... from that calculate the loopgain requiered.

60dB is good enough... just check for the ugf ... 10k is not good.(Typically, rest depends on the transient specs.)

60db ..loopgain or EA gain????

Added after 34 minutes:

Yes, you are right.. output pole(p1) and the pole at EA output(p2) are dependent on each other... and many times very close as well ( when EA is not buffered).

For this you need to make Ro of EA low so that EA pole moves out.
and then add a zero in between p1 and p2.

by the what are the specs u are trying to chase.

can you give me some material on buffer design required for this EA ???

Added after 1 hours 28 minutes:

which consumes less curent for 27pf load...

 

[ashish_chauhan]

Re: LDO questuionair???

I am talking of 60dB loopgain...

I dont as such have any literature on buffer design... but for ur case you start and optimize a simple common drain stuff. 27pf will be driven easily.

What is ur maximum current consumption spec..( total ldo... excluding band-gap)

 

[rajanarender_suram]

Re: LDO questuionair???

I am talking of 60dB loopgain...

So i can keep EA gain to 40db if pass element provides me min of 20dB gain at any cost????

I dont as such have any literature on buffer design... but for ur case you start and optimize a simple common drain stuff. 27pf will be driven easily.

What is ur maximum current consumption spec..( total ldo... excluding band-gap)

i want to design LDO with 60-80uA current consumption excluding bandgap.....

The problem i see with using the driver is as follows:

with 1uF cap output my UGB is 90Meg... so my driver ro =1/gm should be such that the pole provided by it should go atleast beyond 2-3 times the UGB...

than for this condition my driver again takes 1mA of current for my Gm required as above...so I dont see driver as a solution...

is there any EA architechture for LDO so that its EA's current consumption changes with output load-current???

 

[ashish_chauhan]

Re: LDO questuionair???

Yes an EA with 40~45dB gain will do provided ur pass device can give 20 db of gain at any cost...

60-80uA current is good enough. By the way , why are u looking for a UGB of 90meg... Is it not quite high... (may be ur application wants that... just curious) .

I would suggest to first optimize ur bandwidth requirement and then take alook into ur driver...

yes the EA can be desiged such that its bias current tracks the output current

but this is a real good solution for bicmos stuff... in vanilla CMOS it becomes a bit difficult to make tracking that good . but any ways u can do so by adding a current sense transistor in parallel t ur pass device and add its current to the bias of EA.

YOU will find the details of this method in th LDO-book ... its there in this forum..
just make a search ...

hope this could ease ur stuff...

as an ending note I will again say you simply optimize ur UGB and then buffer... no extra stuff will be needed.

 

[rajanarender_suram]

Re: LDO questuionair???

Yes an EA with 40~45dB gain will do provided ur pass device can give 20 db of gain at any cost...

60-80uA current is good enough. By the way , why are u looking for a UGB of 90meg... Is it not quite high... (may be ur application wants that... just curious) .

i know it was high .. when iam using a 1uf output cap the pass transistor output pole is at a bit high freq.. so iam getting the ugb of 90Mhz

thats why in one of my previous posts i asked for decreasing this pole without changing the cap????

I would suggest to first optimize ur bandwidth requirement and then take alook into ur driver...

yes the EA can be desiged such that its bias current tracks the output current

but this is a real good solution for bicmos stuff... in vanilla CMOS it becomes a bit difficult to make tracking that good . but any ways u can do so by adding a current sense transistor in parallel t ur pass device and add its current to the bias of EA.

YOU will find the details of this method in th LDO-book ... its there in this forum..
just make a search ...

hope this could ease ur stuff...

as an ending note I will again say you simply optimize ur UGB and then buffer... no extra stuff will be needed.

thanks...

 

[ashish_chauhan]

Re: LDO questuionair???

what is the pole and zero count of ur LDO? and where are you adding the zeroes?

 

[rajanarender_suram]

LDO questuionair???

2-poles and a zero....zero introduced just after the pole or in between the pole...

what is queiscent of LDO?? is it the current in "opamp + resistive feedback" or only "resistive feedback" only

 

[quaternion]

Re: LDO questuionair???

2-poles and a zero....zero introduced just after the pole or in between the pole...

In between [under condition it is a LHP zero]; as in two stage amplifier!

 

[ashish_chauhan]

Re: LDO questuionair???

yes its the total of opamp and resistive feedback.

whats the queiscent current in ur case...( i think 60~70 uA)

By the way did you think about the stability at no load... or you have some spec for Iload (minimum)...?

Added after 2 minutes:

2-poles and a zero....zero introduced just after the pole or in between the pole...

In between [under condition it is a LHP zero]; as in two stage amplifier!

what do you mean by that? quaternion...

 

[quaternion]

Re: LDO questuionair???

I mean that the Left Half plane zero [that is formed by the ESR & the out Cap] should be between the two poles ; in order to increase the phase margin, similarly like Miller compensation in two stage amplifier.(as nulling resistor miller compensation)

what do you mean by that? quaternion...

I am sorry ; I have replied without seeing past posts & so my reply appeared out of track.
If any thing is wrong, please point to it.

 

[esoteric1]

Re: LDO questuionair???

Here are some appnotes on LDO stability and configurations. Hope these help.

Another file at this link:

 

[rajanarender_suram]

LDO questuionair???

if i had 60db openloop gain and 1st pole due to CL=10uf is at 3K with UGB of 3Meg where should it be ideal for me to keep the zero and next pole due to error amp output??

 

[ashish_chauhan]

Re: LDO questuionair???

you can try to cancel the 2nd pole with the zero or atleast put the zero in between the two poles.

and the best is to keep the 2nd pole out of UGB...

My apologies to quatarnion... I misunderstood you...

 

[quaternion]

Re: LDO questuionair???

you can try to cancel the 2nd pole with the zero or at least put the zero in between the two poles.

and the best is to keep the 2nd pole out of UGB...

My apologies to quatarnion... I misunderstood you...

No need to apology ,My friend ashish.
That is me who was very busy last days (having my graduation exams).

And I want to ask 3 question :
1- If the second pole out of the UGB so here the function of the added zero is to enhance the LDO transient response?

2- Can I look to the transient response from a differnt point of view other than the frequency response ; that is the slew rate of the EA (as it sees large gate cap)& adjust the its SR with the loop stability in the same time?

3-If I am designing a LDO with 0.1V drop out & 5mA max current so what is the suitable range of its ground current (in the voltage divider & EA)

 

[ashish_chauhan]

Re: LDO questuionair???

Hi Quaternion,

The answer to ur first question is yes...

For ur second question again it is yes .... but it is a trade off( faster response means larger current... which means larger bandwidth... which means inclusion of parasitic high freq poles in loop and that means degraded stability.)

For ur third question I can not give you fixed numbers but in a recent design wich i did i had a ground current of few hundred nA in resistive feedbak and less than a uA of ground current in EA and its bias.

But again as i said in one of my previous posts ... decide these numbers depending upon ur transient specs

 

[rajanarender_suram]

Re: LDO questuionair???

you can try to cancel the 2nd pole with the zero or atleast put the zero in between the two poles.

and the best is to keep the 2nd pole out of UGB...

My apologies to quatarnion... I misunderstood you...

if i keep my 2nd pole beyond ugb than it should be atleast at UGB than consider the case with load of 27pf the current will be as large as 200uA

if i tend to use a buffer between the gm required of the buffer again will be large to keep the pole out of UGB as the current in buffer depends on the load capacitance.

 

[ashish_chauhan]

Re: LDO questuionair???

I suggested to keep the 2nd pole out of UGB ... (if possible in ur means)

else u need to place the zero between the two poles.(thats what people usually do)

when ur using the buffer then keep the pole formed at output of EA due to bufer, outside UGB and again compensate by placing the zero between two poles.

In short there are multiple methods to make frequency response better you need to chose which one suits your requierments and avalible resources.