rajanarender_suram said:what is the region of operation of pass element in LDO
ashish_chauhan said:what is the error ur spec allows ... from that calculate the loopgain requiered.
60dB is good enough... just check for the ugf ... 10k is not good.(Typically, rest depends on the transient specs.)
ashish_chauhan said:Yes, you are right.. output pole(p1) and the pole at EA output(p2) are dependent on each other... and many times very close as well ( when EA is not buffered).
For this you need to make Ro of EA low so that EA pole moves out.
and then add a zero in between p1 and p2.
by the what are the specs u are trying to chase.
ashish_chauhan said:I am talking of 60dB loopgain...
ashish_chauhan said:I dont as such have any literature on buffer design... but for ur case you start and optimize a simple common drain stuff. 27pf will be driven easily.
What is ur maximum current consumption spec..( total ldo... excluding band-gap)
ashish_chauhan said:Yes an EA with 40~45dB gain will do provided ur pass device can give 20 db of gain at any cost...
60-80uA current is good enough. By the way , why are u looking for a UGB of 90meg... Is it not quite high... (may be ur application wants that... just curious) .
ashish_chauhan said:I would suggest to first optimize ur bandwidth requirement and then take alook into ur driver...
yes the EA can be desiged such that its bias current tracks the output current
but this is a real good solution for bicmos stuff... in vanilla CMOS it becomes a bit difficult to make tracking that good . but any ways u can do so by adding a current sense transistor in parallel t ur pass device and add its current to the bias of EA.
YOU will find the details of this method in th LDO-book ... its there in this forum..
just make a search ...
hope this could ease ur stuff...
as an ending note I will again say you simply optimize ur UGB and then buffer... no extra stuff will be needed.
rajanarender_suram said:2-poles and a zero....zero introduced just after the pole or in between the pole...
quaternion said:rajanarender_suram said:2-poles and a zero....zero introduced just after the pole or in between the pole...
In between [under condition it is a LHP zero]; as in two stage amplifier!
I am sorryashish_chauhan said:what do you mean by that? quaternion...
ashish_chauhan said:you can try to cancel the 2nd pole with the zero or at least put the zero in between the two poles.
and the best is to keep the 2nd pole out of UGB...
My apologies to quatarnion... I misunderstood you...
ashish_chauhan said:you can try to cancel the 2nd pole with the zero or atleast put the zero in between the two poles.
and the best is to keep the 2nd pole out of UGB...
My apologies to quatarnion... I misunderstood you...
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