ashish_chauhan said:From ur sim results... check the gate capacitance you get for ur pass device. Now the load spec for ur EA becomes this gate cap + miller effect.
so ur amp shud be able to drive this capacitive load.
Also try adding a buffer at output of amp so that parasitic pole dosenot degrade stabilty of loop...
hope this gives you some initial direction for EA design!!
ashish_chauhan said:Yes, you are right.. output pole(p1) and the pole at EA output(p2) are dependent on each other... and many times very close as well ( when EA is not buffered).
For this you need to make Ro of EA low so that EA pole moves out.
and then add a zero in between p1 and p2.
by the what are the specs u are trying to chase.
rajanarender_suram said:what type of transistor for pass-element should i use from my process ..
LVT, HVT, native, nominal
quaternion said:Are you making on-chip or off-chip cap LDO?.
quaternion said:I think for on-chip cap LDO if you make the EA output pole is the dominant you can decrease its current consumption greatly.But you will consume more quiescent current in the pass element to make its pole far enough OR & you will add a zero in the loop.
It all depends on your transient specs as ashish_chauhan said.
rajanarender_suram said:quaternion said:Are you making on-chip or off-chip cap LDO?.
yes
rajanarender_suram said:what is if off-chip cap is used and i make EA pole as dominant one???
ashish_chauhan said:Second option will be better ... the loop shall be easier to stablize.
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