[question]: synopsys dc constraint to cadence gfc

[iamczx]

I use the pearl cmd:

read_dc_script -log aa.log -hpin_log aa_hp.log -retain DAC.dc top_con.cmd
write_gcf top_con.gcf

to convert the dc constraint script to cadence's constraint. But it seems the pearl can't recognize the set_input_delay and set_output_delay command.
so I must modify the gcf by hand. AND I think the set_input_delay should according the arrived_time, set_output_delay according required_time,isn't it?

But I don't know the detail fomat,and the gcfcheck always say the modified gcf invalid..

part of modified gcf

 (CELL ()
    (SUBSET TIMING
      (ENVIRONMENT
        (CLOCK "CLK"
          clk )
        (ARRIVAL (? )   **[b]here I don't know how to descripe[/b]
	7.000 8.700  7.000 8.700 D[15:0] )
        (REQUIRED (?)   **[b]here I don't know how to descripe[/b]
	6.000 8.000 6.000 8.000 dout[63:0] )
        (INPUT_SLEW * 2.900 * 2.900
          rst_n )
        (INPUT_SLEW * 2.900 * 2.900
          din[0] )
        (INPUT_SLEW * 2.900 * 2.900
          din[13] )
        (INPUT_SLEW * 2.900 * 2.900
          test_en )
        (INPUT_SLEW * 2.900 * 2.900
          din[8] )
        (INPUT_SLEW * 2.900 * 2.900
          order_mode )
        (INPUT_SLEW * 2.900 * 2.900
          din[5] )

plz give some advice.
Thanks in advance.[/b]