Question regarding LEF files

[crigri]

Hi@all

First, I'm new to the topic of IC design.
Currently I'm working with soc encounter to do a digital layout. After some hard starting problems i managed to get a routed design with no errors regarding the connectivity - a great thing to me

I did the whole design without using LEF files from the current design (only CORELIB, IOLIB4M & Tech file). Now I'm not sure if i need LEF files (others than the standard ones) and if it is OK to do the design without them. Sorry for my "noobie" questions but thats what I am @ the moment.

I'm looking forward to your helpfull statements!

Kind regards
Cristian G.

 

[iwpia50s]

If you don't have LEF files then you have no physical models of your cells in Encounter. The LEF file tells Encounter the physical characteristics of your library. I'm afraid you hvae some misleading information if Encounter is telling you it routed successfully...unless it created some bogus physical models for you.

 

[crigri]

Morning!

I thought there is a way to do a digital design without using a specific LEF file of my current circuit. What is about the encounter tutorial shown here:

http://www.chiptalk.org/modules/wfsection/article.php?articleid=1

They didn't use LEF files of their design. I found other websites stating the same thing as the before mentioned one. I'm quite confused right now

I'm thankful for any kind of help.

kind regards

 

[ksrinivasan]

HI christian

At many placs i have read that the concept of LEF files is outdated. U can use .lib files instead.
But soc encounter takes both LEF files when u import by RTL/netlist
Iam also confused a bit in this. Hope someone will clear us in this reg

Srinivasan

 

[crigri]

Hi ksrinivasan!

Now I'm happy to hear that I'm not alone
Do u use .lib files? Can you tell me how i can generate them from an existing circuit?

Have a nice day

 

[ksrinivasan]

U cant generate .lif file
This comes as part of the PDK from ur foundry
Try using NCSU Cadence Design Kit
Many other design kits are available from Okhlama State University, Virginia Tech etc

Guys correct me if iam wrong

 

[crigri]

i think u mean .lib files?!?

i use the ams design kit.

 

[ksrinivasan]

sorry i meant the .lef file
just mail me the ams design kit at shrene82(at) yahoo(dot)co(dot)in
i can explain u the other details

 

[raju3295]

Dear cigir,
There must be some thing wrong in ur flow, or u might be missing some of the warnings/errors , check the logs for unknown warnings/errors.

am sure that u can not do pnr of any design without the physical information like in lef.
am wondering how can a .lib can give a physical information , it will have only area but not the dimentaions, which lef has ,,, more over lef will have the blockages for routing i dont think .lib will have this information.

 

[ksrinivasan]

Dear raju

Iam uploading one .lib file
Just explain us the information with ur understanding
It may be helpful to both of us
cadence soc encounter also accepts only .lib files

Srinivasan

 

[raju3295]

hi srinivasan,
Am confused with your question, i did't get wht information your asking for from the .lib u have sent.
If u go thru the .lib u have sent, it contains only the timing and power information and ofcourse the area, but not the physical information, so it is not possibile to do the pnr with only .lib u need .lef aslo.
yep encounter accepts only .libs and .lefs.

Added after 2 minutes:

.libs and .lefs are entirely meant for different purpose,

 

[ksrinivasan]

Sorry guys

I went wrong with with tlf and lef files
My previous post was incorrect
Iam attaching one document downloaded from net
Page 9 may be useful to u

Srinivasan

 

[raju3295]

tlf is a techlef file generally used as a technology specific metlas and vias information,
good document srinivasan,i think it clearly says why we need .lib and .lefs.

 

[iwpia50s]

In the original post crigri said the design was routed successfully. Routing is a physical design step which requires physical models of the cells, otherwise, how does the router know where the pins are on the cells? How does the router know what layer the pins are on for the cells? How would the router know where the obstructions are in the cells? You need a physical library weather it is LEF or whatever. TLF is Cadence timing library format.

 

[raju3295]

yep, thats the confusion now, wht are the library data he has provided while pnr, generally its my assumption that physical information will be provided in the lef format in the cadence, i have no knoledge of tlf, i was confused this with synopsys tech lef .tf file,

 

[ksrinivasan]

Any body has idea about pdk for cadence soc encounter
I started with osu but it has not I/O pads or .lib file is missiing
Any body has crack of tsmc/AMI or any other foundry

 

[iwpia50s]

Check Virage Logic webpage.

 

[crigri]

Hi guys!

Sorry for not answering for the last 2 weeks. I was busy with my studies thus i didn't work.

Not good news for me. I thought that the design could be done as I mentioned above and how it is described in a tutorial I found in the web
http://www.chiptalk.org/modules/wfsection/article.php?articleid=1

I attached the top down design flow how-to which helped me a lot and which is the reason why I thought that I'm fine without the .lef & .def files.

My "job" is to do the digital design. Therefore I get the following files from a designer:
*) .v -> Netlist
*) .sdc -> SDC constraints
*) .conf -> Standard design configuration file from AMS

These are the files I used when I did the design.
Can u tell me the "right" design flow? I'm not sure how to do the design and I absolutely don't know how to get the .lef, .lib and .def files from the above mentioned files.
Do I have to generate the lef.lib & def files from my current design?

It would be great if u could help me to get on with the design.

Thanks a lot!

Edit No. 1:
------------
I have to mention that in the .conf file the following .lef files are included:
*)IOLIB4M_LEF.lef
*)CORELIB.lef
*)C35B4.lef (tech file)

Edit No.2 :
-------------
I think the design flow was OK because the circuit designer only used standard cells from our partner company which already created .lef & .lib files for those standard cells.


kind regards
Cristian G.

 

[raju3295]

yep, lef files are part of the library files like .lib.
Generally in our flow we get those .lefs for each of the cells in the design from the std cell team.

 

[crigri]

Hi rayu3295!

Thanks for your reply!

Now I'm facing a new hurdle namely the combination of the digital layout and an analog layout (import this one into the digital one) and additionally the IO placment.

Can you give me some advices how to do this? If you have any web pages or how-to's reg. this topic please send them to me. This would halp me a lot!

Thank you so far!

kind regards
crigri