question on the timing of scan enable

[owen_li]

Hi.

In my previous projects, we usually use "set_case_analysis scan_enable 0|1" to divide the timing scenarios as: function; scan_shift; scan_capture.

My question is: how can I know the scan_enable to the scan registers meets the timing or not?

As we konw, scan_enable should fall from 1 to 0 when the shift phase is over, and get ready to capture the data.

If there is no timing constraint to ensure scan_enable arriving on time, I think the test will have some problems.

Also, the problem can occur in the at speed test.

Is there anybody who can answer my question ?

Thanks in advance!

 

[owen_li]

Does anybody have some comments?
Can you share some points ?
Thanks!

 

[chakra]

Does anybody have some comments?
Can you share some points ?
Thanks!

does it really a need to look into SE timing? did you build any tree for SE? generally dft tool will have differnces in handling shift and capture sperately , can you give any example?

 

[morris_mano]

In my previous projects, we usually use "set_case_analysis scan_enable 0|1" to divide the timing scenarios as: function; scan_shift; scan_capture.

My question is: how can I know the scan_enable to the scan registers meets the timing or not?
Thanks in advance!

When you say you divide timing scenarios, do you mean you have separate SDCs for function, scan_shift, and scan capture?
Do you use "set_case_analysis scan_enable 0" for function and scan capture, and "set_case_analysis scan_enable 1" for scan_shift?

 

[owen_li]

When you say you divide timing scenarios, do you mean you have separate SDCs for function, scan_shift, and scan capture?
Do you use "set_case_analysis scan_enable 0" for function and scan capture, and "set_case_analysis scan_enable 1" for scan_shift?

Yes. we will have separate sdcs for these three modes.
coz scan_enable is set as a constant in all these three modes, its timing can not be contrained and checked.
Do you think so?

Thanks!

 

[rca]

I guess the PnR tool look at the DRV is respected, after you could add a set_max_delay, to be sure, the latence is "control" for this net, or you add some margin in you ATPG procedure for the load/unload.

An other solution is to have only one SDC without any set_case_analysis without any control on this signal, expect a max delay, and the net will be buffered to respect this.

 

[matter]

Hi Owen_li,

Hi.

My question is: how can I know the scan_enable to the scan registers meets the timing or not?

There is no way to know if scan_enable will meet timing to scan registers. Actually there is no timing requirement for scan_enable. Think about it from a practical point of view in a real chip and how you will shift between modes in a real chip environment. All you need to make sure is is DRCs(max_tran,cap) are met on scan enable lines

No. test will not have any problems without a timing requirement on scan_enable.

 

[ljwfred]

scan_enable is a select between SI and D,
and after shift, before capture the scan_enable is 0,
and clk have a pulse,
then scan_enable is high
and shift out.
does the scan_enable have some relation with the clk?

 

[owen_li]

Hi Owen_li,



There is no way to know if scan_enable will meet timing to scan registers. Actually there is no timing requirement for scan_enable. Think about it from a practical point of view in a real chip and how you will shift between modes in a real chip environment. All you need to make sure is is DRCs(max_tran,cap) are met on scan enable lines

No. test will not have any problems without a timing requirement on scan_enable.

Hi matter.

I find there is setup and hold check between scan_enable pin and clock pin of the register in the .lib file.
So STA tool can guarantee the timing of scan_enable, if the sdc is coded well enough.
Thanks!

 

[matter]

Hi Owen_li,
I checked the libs on my end and I too see setup/hold cheks between SE and CLK pins. But what I have mentioned in my previous post is correct to the best of my knowledge. I have owned full STA setup and done ICC PD work on 5 chips ( > 50M instances). In my opinion, if you are timing scan enable, then you have NOT coded your sdc well enough.
Once again, think from a practical/real chip working/testing perspective or talk with someone in your company who works with the chips after they come back from the foundry. Ask them if it makes sense to time scan enable ? You will realize that it is useless/pointless to time scan enable. I would be very much interested to know if you find otherwise.

Best Regards