question of sigma delta simulation

[chungming]

sigma delta simulation

Hi ~~~

I am a Taiwan student ,study in taipei university of
technology.
I research in SC sigma delta ADC.
I have some problem in simulation that.

First i use cadence spectre transient analysis to simulated then use
fft of wavescan to find PSD.
But the noisefloor is always only -40~-30dB , all
blocks are satisfied spec.
I try to redesign but the same.

Is there has any option in transient analysis i should
choose?

another question is how long the simulation time is
enough ?
(if my spec is clock rate 2MHz , input signal is DC~5KHz)

sorry my english is so poor...
thank for your help ~~!!

 

[arsenal]

what is the resolution in ur design?
if the resolution is small then how much is the quantization noise level? if big then how about the thermal noise in the sc? how about the dc gain of ur opamp?
if everything ok, then you have to increase the # of points in fft and meantime you have to use coherent sampling,that is u have to make sure fin/fsample=Nwin/Nrec,
where fin: input freq, fsample: sampling freq; Nwin: integer # of cycles within the sampling window; Nrec: # of data points in FFt,
and also you can use hanning window.

 

[sunking]

the Vref? the input signal amp?

 

[Irishka]

Matlab (Simulink) and other tools used for system level design and analisys. Cadence IC isn't good choice for this goal.