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[question] minimum DC library requirement

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Advanced Member level 4
May 4, 2004
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Hi, Guys,

we are going to make a standard cell library ourselves for DC synthesis, and come into a question. As we don't want build complex gates like AOI or AIO etc, we want to know what is the minimum requred standard cell set for Design C0mpiler. I searched through the DC manual and referrence, and didn't find related info.

can anyone help me on this topic? if possible please let me know the exact source document of the list.

TNX in advance!


I would say that the minimum standard cells will be very much dependent on your design. Since DC will synthesis based on the available standard cells, insufficient standard cells will result in unoptimised design or even unsynthesizable design.


Thanks for the reply.

here is a short(but not accurate)the DC's minimum requirement definition. The minimum requirement is a set of cells , like DFF, Inv, Nand, Nor etc, that are the basic cells that can let the DC run synthesis, not matter the quality of the result it. If the library does not contain such a set of std cells, the synthesis process can not begin, the DC may complain, let's say, there is no Xor gate, so the mapping can not start.
We want to have a list of the cells, so we can start to build them up.
of course, I can do set_dont_use command to finally find out what are the set.



In theory you can use a nand(or a nor) cell to construct any circuit, so the minimum requirement is only one cell, of couse, the chip's performance synthesised with this library would be good, so, as said, it is dependent on your design, for example, in most library, there are latchs, but in your design, maybe you dont want to use latchs, you neednt design latchs. there are a lot kind diff in most library, for example, posedge trig, negedge trig, with set, with reset, with inventer output, without inventer output, but for your design, maybe only one kinds of diff is necessory, as the same reason, you can design different load cap cells by yourself........


I appreciate your replies very much.

But I think I did not explained my question very clearly.

first let's put the perfermance aside.
and Latch will usually not be used if we talk about design compiler.
And what I am conerning is what are the minimum number of cells that can let the Design Compiler start to run. As I described above, the minimum requirement is that, if there cells do not present in the Lib, DC will even not start to work, and it will complain, for example, "there is no NAND gate in your library".
This is what I want to know. And today I am so busy with current project and forgot to explore this issue.

Thanks again

hi, all,

I found out the requirement today,
at least a DFF, an AND, an Inv and an Or gate are reqired,

thanks for your attention!

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