question in inout port

[hossam abdo]

in vhdl , when i define port as inout and do some operation on it then do the simulation
when i assign it as in (first time) work right
then assign it as out work right
but when assigning it as in again don't work
why this?!

thanks in advance

 

[rca]

by default drive 'Z' to your inout port "inout_port <= 'Z';", and after drive what you want.

 

[ljxpjpjljx]

yes, just like verilog code!