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question in inout port

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hossam abdo

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in vhdl , when i define port as inout and do some operation on it then do the simulation
when i assign it as in (first time) work right
then assign it as out work right
but when assigning it as in again don't work
why this?!

thanks in advance
 

rca

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by default drive 'Z' to your inout port "inout_port <= 'Z';", and after drive what you want.
 

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