[question]: about synopsys dc constraint

[iamczx]

If a module ( clk, b,c),clk is clock ,and b is input port.
Is the following command useful ?

set_min_delay 0.00 -from [get_clocks {CLK}] -through [get_ports {b}]

I think there is no path between the clk and port b ..


thanks in advance

 

[menus]

useful for hold-time check

 

[sunspot]

There is a path between D and CK, this is useful when check the Dff setup and hold.
But I don't think there is a path from CK, though D, and reach some other endpoints

 

[iamczx]

hi members, as sunspot had said,
I don't know why they set the min delay with -through option...
Should it be -to ?
And what the dc will treat the -through in this example? the same result as - to?
thanks in advance