slow lib
but, slow.lib ,typical.lib,fast.lib include standard library,when synthesis with Design Compiler .only need to set target_library slow.lib or tyical,fast.If you set target_library slow.lib,then...Design Compiler select some standard cell from slow.lib according to not only function ,but timing information . timing information from slow.lib is different from fast.lib. when Design Compiler select a cell from slow.lib according cell's timing information for meeting setup/hold demand.but Design Complier select not the same cell from fast.lib according fast library timing infomation.That means gate-level netlist from slow.lib maybe is different from fast.lib .although cell name in slow.lib is the same as cell name in fast.lib.but cell name in gate-level netlist from slow.lib is not the same as cell name from fast.lib.