Question About RTL Compiler

rtl compiler

I would like to ask you a question about RTL compiler..
What is the difference between these two commands:
write -mapped > netlists/DP_FP_ADDER.v
write_hdl > netlists/DP_FP_ADDER.v

and which one is the best in order to use the extracted netlist in SOC Encounter?

Thanks in advance!

rtl compiler what is teh area it report?

write mapped is better!

rtl compiler coding style

I have another question..now that i have to deal with cores that have a clock the script that i run in RTL compiler is the following:

read_hdl fpu_div.v

elaborate

dc::create _clock [dc::get_ports clk] -period 5 -waveform {0 2.5}
dc::set_input_delay 1 -clock {clk} [dc::all_inputs]
dc::set_output_delay 0.5 -clock {clk} [dc::all_outputs]
dc::set_load 0.001 [dc::all_outputs]
dc:: set_drive 1.2 [dc::all inputs]

report timing > reports/repo_DP_FP_DIV
report area >>reports/repo_DP_FP_DIV
report power >> reports/repo_DP_FP_DIV
write_sdc > sdc/sdc_rc_file_DP_FP_DIV
write -mapped > netlists/DP_FP_DIV.v
write_sdf > DP_FP_DIV_sdf

If i have to deal with a core(for example a comparator) which is not clock triggered what do i have to do in RTL compiler? i do not use the commands that concern clock obviously, but do i have to put anything else?

area report after synthesis rtl compiler

both command is same
write_hdl and write -mapped are doing same .. internal alias only

which is best rtl compiler

thanks! in the other question i asked before can anybody help me?

rtl compiler area report

Logic synthesis tool, such as RTL Compiler and Design Compiler, is working according to timing constraint.

Without timing constraint, tool should try to achieve minimal area.

timing constraints

I see.If i take this netlist that is area optimized and use it in SOC encounter will i have information concerning the delay?

rtl compiler write_design

For your first question, I would recommend to use write_design command. This command also generates .conf file which can be read straight away into Encounter.

rtl compiler report

Hi,

I have one doubt??
How to set max_area constraint in RTL compiler?
there is no dc::set_max_area in rc
any RTL Compiler related command for setting the max area constraint?

Thanks in advance

Chaitanya.

reporting timing for rtl compiler

hello ,
can anyone please help me what are the statements of the VHDL language which are permissible in RTL style of coding ?

where can get some more info on tutorials on RTL coding .

What way is the Behavioural style different from the RTL style of coding .

rtl compiler timing constraints

set max_area constraint is fake one. All synthesis tool will work on timing first ,then area. If timing is not met ,there is no reason for max_area 0 constraint.

I seen most of company use max_area 0 constraint. In real world. O area cant achievable.

Aravind