atuo
Member level 3
hi ,all
After I synthesis my design using DC and the timing is met,I get the netlist. I use formality and verify the netlist is equal to RTL.But when I simulate the netlist using NCVeilog,I find the timing is not met, and if I twice my clock period,the simulation result is right.
I don't know why the DC tell me the timing is met but the netlist simulation isn't right before I twice my clock period. I should believe the DC timing report or the result of netlist simulation ?
regards,
atuo
After I synthesis my design using DC and the timing is met,I get the netlist. I use formality and verify the netlist is equal to RTL.But when I simulate the netlist using NCVeilog,I find the timing is not met, and if I twice my clock period,the simulation result is right.
I don't know why the DC tell me the timing is met but the netlist simulation isn't right before I twice my clock period. I should believe the DC timing report or the result of netlist simulation ?
regards,
atuo