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Question about netlist simulation?

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atuo

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hi ,all

After I synthesis my design using DC and the timing is met,I get the netlist. I use formality and verify the netlist is equal to RTL.But when I simulate the netlist using NCVeilog,I find the timing is not met, and if I twice my clock period,the simulation result is right.

I don't know why the DC tell me the timing is met but the netlist simulation isn't right before I twice my clock period. I should believe the DC timing report or the result of netlist simulation ?

regards,

atuo
 

gerade

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did you design pass STA, usually at the synthesis step, only setup time is met, the design may have a lot of hold time violations. that may be the reason.

regards
 

atuo

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Dear gerade,

But I think the hold time violation is not relation with clock period and if there are some hold time violation the netlist simulation is always error.


regards

atuo
 

kslim

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Static timing, I dont think, is a guerantee to dynamic functionality. Would it ?
 

atuo

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But after P&R, you only depend on static timing and FM to ensure your ASIC dynamic functionality and timing.

regards,

atuo
 

AlexWan

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atuo said:
But after P&R, you only depend on static timing and FM to ensure your ASIC dynamic functionality and timing.

Pre-simulation or Post-simulation do dynamic timing verification with simulation annotated the post-sdf file.
STA is only for static path timing analysis.
FM is only for functional verification.

Good Luck.
 

ic_design

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DC only give a simple timing report. You had better pass STA.
 

atuo

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hi all,

I just want to know that can I ignore dynamic simulation if I pass the formality and STA?


regards,
lsong
 

masai_mara

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I think his question is not being correctly addressed. But I also donot know why its so, and would be interested to know the reasons. His problem is with timing violations so please we can exclude formal methods of verification here. But what about STA isnt it supposed to give the violations if any??
 

atuo

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hi horzonbluz,

Why can't I ignore dynamic simulation ?

Thanks for your help.


regards,

atuo
 

spauls

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Formal and STA can't replace the gate simulation(pre-simulation and post-simulation).

1). Formal tools only check the function of the design. It compare design between the different levels, and don't care the timing.

2). STA tools will check the timing of path which we don't set "flase_path" on. Now in SOC design, there are many clock domains. STA normally can't check the path through different clock domains.

So we have to do dynamic simulation, gate simulation.
 

rlogin

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we use STA+FM with about millions gates level design, and do no DTA,and no
problem occurred since now.

to use sta+fm, the key is the design rule. some design rules violations
may cause sta failure, i mean it cannot give the reliable result.

also, you should recheck your dc scripts , such as the path constraints, corner etc.

by the way, did your do an back-annotate simulation with sdf created by dc.
sometimes, the absolute delay in verilog library is much pessimistic.
 

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