Question About Level Translation

[shawndaking]

Hello, I'm Intersted In Solution For Level Translator For Clock Signal.

It Receive Input 1.8v Level From DDS, Clock Generator (After DDS Internal Comparator) Clock Frequency Options Are 2-90MHz

ROutput 3.3v Level (LVTTL)


THANK'S FOR YOU'R HELP !

 

[solvarg]

Hello, I'm Intersted In Solution For Level Translator For Clock Signal.

It Receive Input 1.8v Level From DDS, Clock Generator (After DDS Internal Comparator) Clock Frequency Options Are 2-90MHz

ROutput 3.3v Level (LVTTL)


THANK'S FOR YOU'R HELP !

Please excuse but I do not understand your question?
Do you whant a level translator betwen 1,8V DDS(what is DDS?) and 3,3V LVTTL?

Regards

 

[flatulent]

classical method

One classical method is to use a comparator whose output is in the logic family voltage range you want and set the input compare voltage to half way between the HIGH and LOW voltage levels of the logic family you are wanting to convert.

 

[g579]

The comparator for such high speed case may consists of a differential transistor pair followed by a level shifting transistor. This is a cheap solution too.

 

[btbass]

you can get a single gate open collector buffer to do the job.
74LV07, look in Farnell catalouge.

 

[aglet1000]

I think that an application note written by ON Semiconductor might be helpful here. It is AN1568/D "Interfacing between LVDS and ECL". The web page is onsemi.com

 

[zcq]

Thanks aglet1000!