shawndaking
Full Member level 3

Hello, I'm Intersted In Solution For Level Translator For Clock Signal.
It Receive Input 1.8v Level From DDS, Clock Generator (After DDS Internal Comparator) Clock Frequency Options Are 2-90MHz
ROutput 3.3v Level (LVTTL)
THANK'S FOR YOU'R HELP !
It Receive Input 1.8v Level From DDS, Clock Generator (After DDS Internal Comparator) Clock Frequency Options Are 2-90MHz
ROutput 3.3v Level (LVTTL)
THANK'S FOR YOU'R HELP !