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How to find the maximum data rate of a voltage level translator ic

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newbie_hs

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I am planning to use the NVT2010 in my board for voltage level translation of the Ethernet RMII interface.

We know that the speed of RMII interface is 10/100Mbps.

After checking the datasheet, I am not able to reach a conclusion that this IC will support RMII speed or not. In the TI voltage level translators datasheet, the data rate is directly given.

How can I find the data rate of this IC?
 

Hi,

for a level translator there is no such thing as "data rate".
The "data" transmitted may be RZ, NRZ, or maybe any other.

And for designing the circuit, you don´t need the data rate of the translator either.
All you need to care for usually are "setup" and "hold" timings of the according interface.

And thus you only need to know the delay (and it´s uncertainty) of the translator. (besides the already known ICs).
And this informaton is already given on the first page of the translator´s datsheet: less than 1.5ns propagation delay.
For sure you should have a look for more details at the following pages.

Klaus
 
Hi,

for a level translator there is no such thing as "data rate".
The "data" transmitted may be RZ, NRZ, or maybe any other.

And for designing the circuit, you don´t need the data rate of the translator either.
All you need to care for usually are "setup" and "hold" timings of the according interface.

And thus you only need to know the delay (and it´s uncertainty) of the translator. (besides the already known ICs).
And this informaton is already given on the first page of the translator´s datsheet: less than 1.5ns propagation delay.
For sure you should have a look for more details at the following pages.

Klaus
But in digikey,selection filter you can see a column for data rate.
 

Hi,

you are right.
I opened the 74LVC1T45 datasheet. Even they write about data rate.
They even give 5 different data rates ranging from 60Mbps to 420Mbps depending on logic levels.
We don´t know about your voltage levels, nor does digikey know. So the digikey given 420Mbps most probably don´t apply for your circuit.

Indeed they don´t give any definition about data rate. Thus I call it a "marketing value".
I´m not saying that the value is wrong, one might achieve the given data rate .... but only with suitable test conditions.
For an RMII interface the value may be almost meaningless.

True data rate surely depends on many things. Even cable length.
The least critical may be an asynchrounous NRZ interface (UART style). Here the delay is non critical.

I doubt that the RMII is similar "tolerant" regarding delay timing.
For you to be sure I can only recommend one thing: Read the timing specifications of all involved parts and do the timing calculations on your own. Excel could be of help.

Klaus
 

@OP

Max data rate :


1685706616373.png



Regards, Dana.
 

We know that the speed of RMII interface is 10/100Mbps.
No. RMII transmits 50 MBPS per data line with 25 MHz clock (DDR). The level converter is primarily designated for open drain I2C interfaces.
The datasheet states 33 MHz data rate, but only achieved with strong pull-ups that are probably not supported by RMII peers.

I wonder why you need RMII level translation at all?
 

It can be difficult to determine a data rate from prop delay
if it's a simple "taper chain" accounting for most of the
Tpd - it's a "pipeline" that may accommodate multiple
reversals down its length (if length is large relative to
per-stage Tpd).

Drive strength and Cstray are more likely to "collapse
the eye". Have seen even 80MHz fail to "kiss the rail" on
10mA 3.3V CMOS outputs. Always worse at low supply
and high temp, so constraining those might give you
slack (look at back material in DS, for temp and supply
curves).

A well formed eye ought to have equal parts allocated to
rise, flat-top, fall, flat-bottom sub-intervals (at 50% duty).

Now if 100MBPS is NRZ then bit time is 10ns and you
might get a usable eye out of 5ns rise, 5ns flat-top.
But that means a pretty good positioning of input clock
relative to input data, besides just clean data waveform
switching. And you probably want control of PCB parasitics
(and to de-sandbag any datasheet delay, rise/fall, load-case
"stuff" attending the datasheet specs / conditions) to assess
whether the part can hang.
 

Hi,

you are right.
I opened the 74LVC1T45 datasheet. Even they write about data rate.
They even give 5 different data rates ranging from 60Mbps to 420Mbps depending on logic levels.
We don´t know about your voltage levels, nor does digikey know. So the digikey given 420Mbps most probably don´t apply for your circuit.

Indeed they don´t give any definition about data rate. Thus I call it a "marketing value".
I´m not saying that the value is wrong, one might achieve the given data rate .... but only with suitable test conditions.
For an RMII interface the value may be almost meaningless.

True data rate surely depends on many things. Even cable length.
The least critical may be an asynchrounous NRZ interface (UART style). Here the delay is non critical.

I doubt that the RMII is similar "tolerant" regarding delay timing.
For you to be sure I can only recommend one thing: Read the timing specifications of all involved parts and do the timing calculations on your own. Excel could be of help.

Klaus
"We don´t know about your voltage levels, nor does digikey know. So the digikey given 420Mbps most probably don´t apply for your circuit." My voltage levels are 3.3V and 5V
--- Updated ---

No. RMII transmits 50 MBPS per data line with 25 MHz clock (DDR). The level converter is primarily designated for open drain I2C interfaces.
The datasheet states 33 MHz data rate, but only achieved with strong pull-ups that are probably not supported by RMII peers.

I wonder why you need RMII level translation at all?
"I wonder why you need RMII level translation at all" In my board communication between a Microprocessor and microcontroller is happening via ethernet (RMII MAC TO MAC communication).

The microprocessor is working at 3.3V and microcontroller working at 5V.
 
Last edited:

If that's all there is to the problem (bang-bang level translation)
then you don't need to wrap all the comm-standards "stuff"
around it. Just go for the cheese. Start with the broad line logic
suppliers. Level translators have been part of "logic families"
even before VDD=3.3V "was a thing".
 

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