question about IC designflow

[hqqh]

Hi,
i'm a little bit confused about the design methodes for ICs.
as i know there are a Top-Down and a Bottom-up design flow.
if i have a top-down design flow like this:

design specification --> behavioral description --> rtl description -->
functional verification and testing --> logic systhesis -->
gate-level netlist --> logical verification and testing-->floor planning-->
physical layout --> layout verification --> implementation

My question:
is it possible to get a transistor-level netlist when the gate-level netlist is created (i want to execute spice simulations)? can somebody provide me a good link about IC design methodes?

thanks in advance,
hqqh

 

[eda_wiz]

I also have the same doubt ? where will we get the Transistor level netlist from ???

tnx

 

[kbulusu]

Hi ,
First comming to your doubt, it is very much possible to generate Transistor level netlist even when u have gate level net list. Actually u need an transistor level simulator for the job u wanna do...

i know a tool called Star-SimXT which uses Milkyway database to reduce the size of the detailed standard parasitic format (DSPF) files. The transistor-level simulator takes the parasitic models from the DSPF files and back-annotates them into the HSpice netlist. now u can do full spice level simulations.

if i'm wrong, do corrrect me . thx

kiran.

 

[okguy]

HSIM comes with a little software called v2s.
It convert Verilog to Spice.
HSIM can read DSPF, so, it sound to be your solution.

OkGuy?

 

[visualart]

The IC flow of Cadence is the best,
u may get some help from www.cadence.com

 

[philewar]

Hi,
My question:
is it possible to get a transistor-level netlist when the gate-level netlist is created (i want to execute spice simulations)? can somebody provide me a good link about IC design methodes?

Upon to your question, I think the answer is Yes.
First, let's assure we are talking about std cell design flow.
Most vendor provide spice netlist for every cells, i.e. you can get transistor level netlist by merging those std cell spice netlists into gate level netlists. Normally, we get schematic this way when doing lvs for a full std cell p&red design.

Thx. Pls correct me if sth. is missed.

Best,

philewar

 

[z81203]

normally, for digital ic, gate level netlist is enough to run digital simulation. for mixed & analog ic, you would need transistor level netlist to run spice simulation.
if vendor provide you gate & transistor level library, you can do it. if not, you can get transistor level netlist after p&r layout.

 

[ttspice]

No matter which flow you adopt, as long as you can get your layout ready, you can use LPE tool to extract transistor-level netlist and parasitic RC (optional). The netlist can be simulate with any spice simulator. Usually we do it for smaller mixed-mode IC which needs accurate simulation with parasitic RC which is generated by layout. For logic design, use HDL simulation in gate-level is enough.

 

[stewmal]

If you are doing a straightforward digital design you shouldn't need to do spice simulations.

If you are doing a digital PLL, DLL, or anything that isn't latch to latch or FF to FF then you might want to simulate with SPICE models.

stew

 

[lassyy]

Yes, you can, but first, you must have a spice/CDL netlist library of all units, if your gate level netlist is verilog netlist. you must translate it to spice or CDL netlist. general, i use "nettran" to do this, at last, combin the two netlists together.

 

[zoz86]

u can got the dspf file from many
rc-extractor and then sim it to solve
this problem.
But as i know, most rc-extractor can
only supprot flaten dspf format well,
poorly hierarchical format

 

[vsop]

Actually, you have made a q-level netlist while performing the layout verification (I mean LVS). But getting back the q-level list is fully dependend on what flow you adopts. If your company have your own library, yes, you can get the q-level netlist; on the other side, you will never see that if you are cooperating with the ASIC house. But I have no idea about which tools are able to extract the SPICE q-level netlist.

 

[cawan]

to large system synthesis, gate level is sufficient to perform related analysis and simulation. transister level is too complex to be consider for IC design flow regarding to the asic or fpga technology. of course some of the critical event such as metastability, race condition and etc. should be considered, but transister level is not suitable to be go into the detail of ASIC design. instead, system design is more important to be emphasis in ASIC design. if i am wrong, please advice.

 

[hqqh]

transistor level simulation

HEllo,

thanks for your answers. they were very helpful.

to cawan: in the patent US06493850 from Texas Instruments "Integrated circuit design error detector for electrostatic discharge and latch-up applications" a tool is described that can simulate entire ICs on transistor level to detect over voltages. and therefore i asked, because i thought in a standard ic design process there is a top-down design flow. if yes you have only the gate-level netlist, which is not useful for transistor level simulations.

sorry, if the patent document is not attatched. i have problems to attatch files in elekroda. i dont know why!!!

 

[hqqh]

3 times the same file

Hi,
the 3 files in the post above are the same files. sorry for that. my browser (o.p.e.r.a7.01) asked me three times whether the file should be sended to elektroda-forum and i could only proceed if i click yes.
had anyone similar problems?

greetings,
hqqh

 

[cikyen]

As long as you have a spice netlist library, then you can always convert your verlilog netlist to a spice, transistor format by using nettran in Hercules.

But, bare in mind that, HSpice can not take in large design. It will never return the result to you if you give it a full design (more than 1K gates). You might want to just extract the critical path for your HSpice simulation. You can always do that by using PT-SI from Synopsys.

 

[maniasonic]

why do you want to simulate your digital design under spice? it will be quite slower and doesn't make any sense. normally, a gate level simulation is enough for even hi-speed designs.

 

[sandusty]

We can get the transistor level ckt from back-end tools after finish the p&r.

But I am wandering how can we put back the wire RC into the spice netlist? Even we exrtact those RC, what's the wire model tools can put the wire RC back??? L model? E'lmore model? Transimission model?

 

[libo]

i think designing from gate level to transistor leve is a real hard job if no cad tools. The solution is reuse the std cell.

 

[tom123]

In digital IC design, we generally use sdtandard cell lib to realize our system.

The minimal parts that we can deal with is the gates in lib,

so, I think that transistor level netlist is hard to get.

Hi,
i'm a little bit confused about the design methodes for ICs.
as i know there are a Top-Down and a Bottom-up design flow.
if i have a top-down design flow like this:

design specification --> behavioral description --> rtl description -->
functional verification and testing --> logic systhesis -->
gate-level netlist --> logical verification and testing-->floor planning-->
physical layout --> layout verification --> implementation

My question:
is it possible to get a transistor-level netlist when the gate-level netlist is created (i want to execute spice simulations)? can somebody provide me a good link about IC design methodes?

thanks in advance,
hqqh