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question about combinational logic

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ustc23

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I have one basic question about combinational logic
To implement any combinational logic, what is the minimum set of logic gate? Why there are so many types of standard cells in the library?
Thank you!
 

avimit

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multiple gate offers choices for the synthesis tool. a mux can be implemented by and gates and inverters, but when a mux is present in the library, it will be efficient in terms of area, power, speed, as compared to a mux which is synthesized using and gate and inverters. Hence so many cells in the library.
Kr,
Avi
 

Nir Dahan

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To implement ANY logic function you need only NAND gates or only NOR gates.
NAND (as well as NOR) comprise of a "complete boolean system"

The reason you have many more variants of gates is that nobody said that implementing everything with NANDs is the most efficient way transistor for transistor.
By efficient I do not mean only regarding one aspect like power or area. The different flavors of gates in a library give the synthesis tool the necessary freedom to optimize for transition, capacitance, driving strength, timing, power, area etc etc.

ND.
https://asicdigitaldesign.wordpress.com

Added after 2 minutes:

Oh one more thing, for understanding digital systems and FSM theory, I recommend the best book around by Kochavi.

it is from 1978 but a must read - it is NOT in anyway outdated!
https://www.amazon.com/Switching-Au...07/ref=sr_11_1?ie=UTF8&qid=1221037645&sr=11-1

ND.
https://asicdigitaldesign.wordpress.com
 

ustc23

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Thank you very much! Have a nice day^_^
 

ASIC_intl

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Hi avimit!
Sometime back I had questions to you. The comments and questions are agin printed below. This was related to the discussion of unit area when we get the area report.

In the library no unit of area is defined.

Is it generally true that inverter is always the basic cell for unit area in libraies of all fabrication foundries?

There are many inverters in a library with different areas. There are inverters in the library that have area less than 1.0.

What is the basic unit cell for calculating area among all these inverters of different areas?

When it is said 0x drive, 1x drive. What does it mean?

Does it mean driving capability interms of a basic gate? What is the basic gate then? What is the exact driving capability of that basic gate?
 

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