Question about 2-bit variable in Verilog

[feel_on_on]

reg a [1:0] a is a 2-bit variable


then...if (a == 1'b0)
state = 6'b100000 ;

else state = 6'b011101 ;

2-bit variable == 1-bit value : 1'b0 ,it affect the design?

 

[rberek]

Re: Question on verilog

If "a" is either 00 or 10, it will satisfy the first part of your if statement.

So if you did not intend that, it has affected your design

 

[5life]

Question on verilog

Agree with rberek!

Take care of it , coding style is a good thing.