nathanpk
Newbie level 3
Query in transition delay after clock tree synthesis
Hi,
I am new to physical IC design and I am working on CTS now. After CTS when I checked the clock transition time, it seems that rise transition time is different from fall transition time. Can anyone tell me why its different?
Thanks!
Hi,
I am new to physical IC design and I am working on CTS now. After CTS when I checked the clock transition time, it seems that rise transition time is different from fall transition time. Can anyone tell me why its different?
Thanks!